Questions tagged [routing]
Questions about the routing of printed circuit boards (PCBs) which involves the placement of tracks on the board. It may be performed manually, but many PCB CAD programs provide an autorouter to assist in the process.
382 questions
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Rule for 5W Routing Differential Pair
I am working on a high speed design. To reduce the cross talk between the signals I need to implement a 5W rule (which means that the spacing between the signal pairs must be
a minimum of 5 times the ...
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Altium designer bus duplicate net names in hierarchical schematic
I have a Design with several subsheets. I'm having issues connecting i2c buses. Two sheets contain buses named IIC_SDA[1..25] and IIC_SCL[1..25].
When both of these sheets are placed inside the top ...
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Altium, via splitting instead of through-hole via
My question is regarding vias/routing. As you can see in the picture I want to have a via from the top to the bottom layer. The problem is that Altium always splits these, in fact through-hole via, ...
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Handling Dead Copper in Internal Power Planes [duplicate]
I am working on a 4-layer PCB (1200 mil × 1000 mil) with TOP, GND, 3.3V midlayer, and Bottom. I encountered a situation where, if I pour the polygon all over the entire midlayer while removing dead ...
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PCB design for audio compressor – THT routing, GND plane and power tracks
I’m working on a PCB design for an audio compressor. I don’t have much prior experience with PCB layout, so I’d really appreciate any advice or feedback you might have.
I’ve attached the layout of my ...
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DDR4 bit, byte, nibble swapping
I’m working on a DDR4 PCB layout and want to confirm the allowed rules for bit swapping, byte lane swapping, and nibble swapping, especially when ECC or CRC is enabled.
From what I understand so far:
...
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Questions Regarding PCB wiring from Schematic Design
H-Gate Driver in use: [https://lcsc.com/product-detail/Gate-Drivers_Infineon-IR2101STRPBF_C2956.html]
The general issue is connecting components in general on a PCB and if specific tracing is needed ...
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How to best route VCC over "pre-magnetic" phy: via or 0R?
I am routing the KSZ8794CNX (https://www.mouser.com/datasheet/2/268/KSZ8794CNX_Data_Sheet_DS00002134-3444409.pdf) in a two layer PCB, and I might need to route its 3.3V and 1.2V through the "pre-...
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In this scenario, is it better to have a continuous GND plane or a break in the middle?
I'm implementing a high power converter on a PCB (8A/300W) and I'm unsure which power plane design is better. In this example, I'm unable to move the terminals or any components.
Let's use this PCB ...
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DDR3 UDIMM dual rank stick design considerations
I am designing a standard 240 pin DDR3 UDIMM PC ram stick for learning purposes. I did quite a lot of research on the DDR3 architecture and PCB layout, but there are still some questions that I can ...
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DDR3 in a fly-by routing
I recently completed fly-by routing for 2 x DDR3 and a Zynq 7000 chip by studying their app notes or general notes on how to do fly-by routing. Now that I finished the routing then I started having ...
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IC power pins are the same voltage, can I route through both decoupling capacitors into the pins?
I am having some trouble with routing the connections to a BMP390 barometer. In order to make more space for the SPI CLK line, I was wondering if it would be OK to route through the decoupling ...
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Routing trace after existing a via
In PCB design, 90-degree angles in trace routing are generally discouraged due to potential issues with signal integrity, impedance discontinuities, and fabrication defects.
However, I am wondering if ...
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Best layout practice for unused input pins on CMOS gates (SNx4HC86)
While routing a layout with an SN74HC86, I came across the "Layout Example" from Texas Instruments (S. 13, Figure 11-1):
I am woundering, if there is any reason Texas Instruments is ...
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Low layer count with blind/buried vias VS High layer count with regular vias
I am designing a PCB that contains multiple peripherals (USB super speed - Ethernet - HDMI...)
I am in the middle of the design phase and i reach 12 layers with regular vias, but I am still not able ...
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