Questions tagged [ddr3]
The ddr3 tag has no summary.
132 questions
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DDR3 UDIMM dual rank stick design considerations
I am designing a standard 240 pin DDR3 UDIMM PC ram stick for learning purposes. I did quite a lot of research on the DDR3 architecture and PCB layout, but there are still some questions that I can ...
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Risetime of DDR3 clock signal AMD Xilinx
I am using ZYNQ7010 SoC from Xilinx (AMD) to control two DDR3 memories with fly by routing. I am trying to run simulation to check signal integrity overall. Where can I find risetime information for ...
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DDR3 potential signal integrity issue
I am currently in progress designing SoC based on AMD Zynq7010 with two DDR3 memory (MT41K256M16TW-107IT:P). I am utilizing fly by routing. Upper memory is 2nd DDR3 memory and lower memory is 1st DDR3 ...
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DDR3 in a fly-by routing
I recently completed fly-by routing for 2 x DDR3 and a Zynq 7000 chip by studying their app notes or general notes on how to do fly-by routing. Now that I finished the routing then I started having ...
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Spartan-6 MIG DDR3 Write Issue: Incorrect DQS to CK Alignment
I'm implementing a DDR3 controller using Xilinx MIG on a Spartan-6 XC6SLX16-2FTG256 FPGA. The DDR3 memory I'm using is MT41J128M16. The issue is that, during write operations, the upper byte (DQ[15:8])...
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AM335x ICE EVM Rev2.1 it seems the datasheet, BOM, and schematic don't align more details down is there any s MT41J128M16JT-125 (84-ball FBGA package)
In TI’s document for the ICE design, they specify a 2 Gbit DDR3 SDRAM with part number MT41J128M16JT-125 in an 84-ball FBGA package. However, when searching on Micron’s official site and distributor ...
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DDR3 Termination Resistors Messing Up SI?
Do these results make any sense? Or is there perhaps a bug in the Altium Designer Keysight SI plug-in?
I'm testing the new Altium SI plug-in by Keysight. In particular, I'm curious about using it to ...
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DDR with ARTIX 7 is not initialaizing
We are using Artix7 200T in our design.
We are using two independent DDR3L (MT41K512M16VRP-107 AAT) interface in our card.
Both with 8Gb capacity with 16 bit data width.
Both DDR is completely ...
user398283
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Ferrite bead vs feed through capacitors for LPDDR4
I am designing a TI's AM6442 processor board
I am using SK-AM64x their development board as desgin reference.
There are two version an older and a newer
Old version schemtatic:
New version ...
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LPDDR4 layout, should we avoid having signals in same byte group on different layers?
Is it a bad idea to route intra byte DQx on different layers?
I am trying to interface AM6442 to LPDDR4 16bit. I have followed every constraint in TI's DDR layout guidelines to the letter, ...
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Please Review my PCB stackup
I am developing an AM6442 SOM.
This is PCB layer stackup
This my layer assignments:
L1: Signals - Low Speed (UART, QEP, PWM, DeltaSigma ADC, GPIO, JTAG)
L2: Ground Plane
L3: Signals - HighSpeed ...
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Is my meander a bad idea?
Autodesk Eagle's Meander:
My compact meander:
How bad of an idea is it to use "My compact meander" meander instead of the Eagles's version? The Autodesk Eagle's meander tool is very bad, ...
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DDR3 Address Line Length Matching Tolerance
I'm looking at a design where the maximum difference between two address signals of a DDR3 memory is 306ps. The frequency is advertised to be 800MHz, so it seems that one address signal would arrive 1/...
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Does DDR3 master clock need to be longest trace in general?
I'm working on my first PCB which incorporates DDR3L memory with an STM32MP157AAB3 processor. I've been following ST's DDR3 guide from AN5122 and I came across something which I found odd and which my ...
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Choosing DDR3 for Zynq-7000 (XC7Z010-1CLG400I)
Looking at the AC characteristics of the Zynq-7000 it is said that the maximum data rate of the -1 speed grade is 800Mbit/s (it is also specifically mentioned that the clock frequency for data ...
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