Routing trace after existing a via

Question

In PCB design, 90-degree angles in trace routing are generally discouraged due to potential issues with signal integrity, impedance discontinuities, and fabrication defects.

However, I am wondering if this rule specifically applies when exiting a via, particularly when the trace on the top layer makes a 90-degree turn relative to its previous direction before entering the via.

My questions are:

• Is it acceptable to have a 90-degree angle immediately after a via, relative to the top-layer trace?
• Are there situations where this would not be an issue? (e.g., low-frequency signals, power traces, etc.)
• For high-speed signals (e.g., USB, PCIe, LVDS), are there specific recommendations for via exit routing?

Answer 1

Indeed it is discouraged to have 90-degree angles in trace routing. It would be best to have no angles or discontinuities at all. But in real life, we need to make compromises.

So there's no general answer to your question. You would need to define the exact setup, do a simulation or measurement to find out how much your via exit strategy impacts the signal integrity.

As long as you are not in the high frequency, high precision or secret service business, you simply do not need to care about such stuff.

Answer 2

I agree with the answer by @Stefan Wyss -- reality is imperfect, and via exits will not be your biggest problem.

What is your alternative to a 90 degree exit? Are you planning to make the via physically resemble an hourglass instead of a tube? That could work if you're doing a giant-scale model. It also sort of describes some microvias, if you're willing to pay for that.

My first recommendation is to figure out how large a feature has to be before it matters to your actual rise and fall times; you may well decide that you don't have to worry after all.

For sufficiently high speed, the recommendation is to avoid vias. If you can't do that, minimize them (have fewer). Try to avoid stubs, which might mean back-drilling (or controlled-depth drilling) if you aren't going all the way from top to bottom or using blind/buried vias. Make sure the return current has its own via nearby, if that will also be switching layers. (Some designs use multiple ground vias.) There are materials with tighter tolerances. Maybe even consider impedance matching when sizing your vias.

If you're being very careful, use a 3D simulator and try to keep the impedance through the via the same as it is in the traces. This won't be modelled as well as you hope, in part because the capacitance will change when you're passing a plane vs dielectric.

But honestly? How sure are you about, for example, the uniformity of thickness of your via walls? The exact drill registration? (Fabs like Sierra Circuits talk about recalibrating to account for differential shrinkage across the same panel.) Are you worrying about effects that will be swamped by manufacturing tolerances?

Answer 3

In PCB design, 90-degree angles in trace routing are generally discouraged due to potential issues with signal integrity, impedance discontinuities, and fabrication defects.

For high speed design over ~100MHz this is true, otherwise the electrons won't "run over the edge"

In PCB design, 90-degree angles in trace routing are generally discouraged due to potential issues with signal integrity, impedance discontinuities, and fabrication defects.

Fabrication defects used to be an issue with masking. With impedance curves are recommended to keep the path lengths the same and also to reduce RLC effects in meanders. Again these effects are only worrisome in the 100MHz+ as trace cross capacitance in lower than pFs come into play. (higher frequencies jump across smaller capacitors better)

For high-speed signals (e.g., USB, PCIe, LVDS), are there specific recommendations for via exit routing?

A better thing to do is make sure the trace length is the same on LVDS, but only within the specs of the line. Most differential traces will give you a matching length and it's best to match the length of the lines. If switching layers make sure you account for the via delay and also the length difference. Most of the time the trace width will vary from inner layer to outer layer. If you are routing above ~2GHz you'll need to run the design through a 3d or 2.5d field solver and make sure none of the routing is causing an issue with signal integrity.