How to pass specific array index as input in a module in Verilog?

Question

I have a 4:1 Mux as follows:

module mux4_1 (input [31:0]A, input [31:0]B, input [31:0]C, input [31:0]D, input sel[1:0], output [31:0]Y);

wire mux1o, mux2o;
mux2_1 mux1 (A, B, sel[0], mux1o);
mux2_1 mux2 (C, D, sel[0], mux2o);
mux2_1 mux3 (mux1o, mux2o, sel[1], Y);

endmodule

In another module I have an array F of length 4 as input and need an instance of the 4:1 mux in this module with elements F[1] and F[3] of F as selectors. How can I specifiy this when declaring the instance? Surely this code below does not work, but it should illustrate what I am trying to achieve.

module someModule (inputs... F[3:0], outputs...);
 // some code...
 mux mux4_1 (A, B, C, D, F[1]F[3], Y);
endmodule

{F[1],F[3]} but make sure you got the order the right way around. Normally the select goes MS to LS: {F[3] , F[1]} — Oldfart
– Oldfart, Commented Apr 6, 2020 at 11:26

Nicolas Antoine · Accepted Answer · 2020-04-08 16:54:28Z

1

To create you selector signal, you can simply concatenate the signal you need from your array.

wire [1:0] selector;
assign selector = {F[1], F[3]};

// selector is a 2 bit vector where 
// selector[0] == F[3]
// selector[1] == F[1]

A faster implementation would be in your case:

module someModule (inputs... F[3:0], outputs...);
     // some code...
     mux4_1 myInstance (A, B, C, D, {F[1], F[3]} , Y);
endmodule

In this case, the LSB of the selector is F[3] and its MSB is F[1]

answered Apr 8, 2020 at 16:54

Nicolas Antoine

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