How to pass array structure between two verilog modules

Question

I am trying to pass a array structure as reg [0:31]instructionmem[0:31] between two modules.

I coded it as follows :

Module No 1:

       module module1(instructionmem);
            output reg [0:31]instructionmem[0:31];
            ------------------
            ----lines of code---

            ---------------
       endmodule

Module No 2:

         module module2(instructionmem);
           input [0:31]instructionmem[0:31];
           --------------------------------
           -----line of code---------------
           -------------------------------
           endmodule

Testbench:

     module test_bench();
     wire [0:31]instructionmem[0:31];

     module1 m1(instructionmem);
     module2 m2(instructionmem);
     endmodule

I am getting errors for this implementation. So how can we send such array structures ?

have you tried defining as output/input reg/wire [31:0]instructionmem[0:31];, ie switching the order of the width definition. — Morgan
– Morgan, Commented May 4, 2013 at 2:20
I believe this is only supported in SystemVerilog, have you enabled SystemVerilog mode sometimes by using .sv file extension or running with a -sv flag — Morgan
– Morgan, Commented May 4, 2013 at 9:07

CliffordVienna · Accepted Answer · 2016-03-10 10:28:00Z

This is not possible in Verilog. (See sec. 12.3.3, Syntax 12-4 of the Verilog 2005 standard document, IEEE Std. 1364-2005.)

Instead you should "flatten" the array and pass it as a simple vector, e.g.:

module module1(instructionmem);
  output [32*32-1:0] instructionmem;
  reg [31:0] instructionmem_array [31:0];

  genvar i;
  generate for (i = 0; i < 32; i = i+1) begin:instmem
    assign instructionmem[32*i +: 32] = instructionmem_array[i]; 
  end endgenerate
endmodule

module module2(instructionmem);
  input [32*32-1:0] instructionmem;
  reg [31:0] instructionmem_array [31:0];

  integer i;
  always @*
    for (i = 0; i < 32; i = i+1)
      instructionmem_array[i] = instructionmem[32*i +: 32];
endmodule

module test_bench(instructionmem);
  output [32*32-1:0] instructionmem;
  module1 m1(instructionmem);
  module2 m2(instructionmem);
endmodule

Collectives™ on Stack Overflow

How to pass array structure between two verilog modules

1 Answer 1

Comments

Linked

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Linked

Related