959 questions
0
votes
0
answers
91
views
Ostensibly incorrect synthesis by SynplifyPro, result differs from Icarus Verilog & Verilator
I stumbled upon perplexing hardware behavior in the following simple circuit, provided here verbatim:
/// Given an WIN-bit signed input, truncates the most significant bits to produce a WOUT-bit ...
- 1,318
1
vote
1
answer
95
views
Is it possible to verilate and compile big generate with verilator?
I'm designing game of life in Verilog. The design consist of simple cell that been generated in grid with generate.
gol_cell.v :
module gol_cell (
input clk,
input rst,
input [...
- 3,901
3
votes
1
answer
107
views
Verilog full adder
This is the Verilog question. I have written the code according to the image, but I'm getting mismatch in the output, can I get some assistance?
module add1 ( input a, input b, input cin, output ...
- 73
0
votes
1
answer
163
views
CocoTB: How to test interaction between two Verilog modules
What is a good way to test the interaction between two (or more) modules using cocotb?
For example, say we have a transmitter (TX) and receiver (RX) module, and we want to test them together (e.g., RX ...
- 29
4
votes
2
answers
122
views
Issue with driving an LED matrix using an FPGA (Verilog)
I am trying to run an LED matrix using an FPGA. The specifics are a TinyFPGA BX, wired into this board (driver chip datasheet), connected to this screen. Before this, I managed to drive this matrix ...
- 43
-1
votes
1
answer
126
views
Bluespec Verilog - polymorphic vector type
In Bluespec System Verilog I would like to have a Vector of the same module but with different type parametrisations. I am trying to do something along the lines of this:
Module#(1) m1 <- mkModule;
...
- 33
0
votes
0
answers
81
views
How can I transform yosys gate primitives (e.g. $reduce_or) to simple gates and then pattern match those to more complex Verilog cells?
I am new to Yosys, and I want to optimize arbitrary netlists to a set of complex cells.
For example's sake, let's consider an or-reductions:
red_or3x1_test.v
module test (A, Y);
input [6:0] A;
...
- 11
1
vote
1
answer
83
views
Error (10170): HDL syntax errors in Quartus (HDL)
Can anyone see what is wrong with my code?
I copied the code from the article, but the code in it works without errors.
These are the errors:
module sqrt #(
parameter WIDTH=8, // width of ...
- 13
0
votes
1
answer
131
views
8 way OR gate in Hack's HDL language
i'm a first year computer science student and i've found myself stuck on one particular part of the assignment.
We are tasked to create several gates in hack's HDL in various ways. I had little to no ...
1
vote
1
answer
79
views
How does the signal value change if it's own value is used to calculate it?
I am a am currently studying VHDL and I have encountered an interesting problem.
I have created an entity Sklop with the architecture Beh2:
entity Sklop is
port (
x : in bit;
y : in bit;
...
- 51
0
votes
1
answer
265
views
Errors in nand2tetris hardware simulator
I am currently in a course that is covering nand2tetris tools and such, and I got my first homework to implement a few chips but none of them seem to work, I get an error msg for every chip I try. ...
- 13
-2
votes
1
answer
50
views
Inverting pin value in physical constraints (Gowin EDA)
I've recently bought a Tang Mega 138k Pro fpga board. it contains some peripherals (switches, led, ...) that are active low. Is there any way to invert the pin in physical constraints file so i don't ...
1
vote
3
answers
89
views
Writing recursive code to find unmatched parenthesis in a string?
I'm currently working on some code in SystemVerilog to find matching parenthesis in a string. The code takes in an array called str that holds n characters, each 4 bytes long. The string will have ...
- 11
1
vote
2
answers
117
views
Verilog assignment using vectors
I am attempting to assign data from one wire to another wire in Verilog using vector subscripting. This is the simplest implementation that I could think to write to demonstrate the problem I have. ...
- 73
0
votes
1
answer
98
views
Sub bus of an internal node may not be used. Nand2tetris hdl error while making the RAM8 chip in project3
I used 16 DMux8Way chips to take the 16 bit input and put in a temporary variable according to the address. The naming convention used to assign the temporary variable is (p, q, r, s, t, u, v, w, x, y,...
- 3