3,628 questions
2
votes
1
answer
44
views
Why is my simple ARM7 data memory on Verilog failing tests?
I'm implementing a simple ARM7 in Verilog and am currently in the process of creating a simple data memory. I've come up with something like this:
// very simple sdata implementation with 1mb~ memory
...
- 191
0
votes
0
answers
67
views
Getting fatal during simulation while trying ivoke get in agent
I’m facing a UVM_FATAL during the build_phase when the reg_agent tries to fetch its configuration object from the UVM config database.
Below are the code snippets I’m using and the corresponding ...
- 1
1
vote
1
answer
86
views
Random stability with non-random object
I have a simple example for random stability in QuestaSim.
module sv_rand_stability;
class dummy;
rand int data;
endclass
initial begin
dummy d;
$display("%...
-1
votes
0
answers
35
views
How does `case inside` handle z and x and is it different from casex and casez? [duplicate]
How does case inside treat z and x? And how does it compare to casez and casex?
The LRM describes all three, but I couldn't find a comparison of them or a recommendation for either.
https://cjdrake....
- 5,566
1
vote
2
answers
88
views
Is conditional bracket pairing possible?
In SystemVerilog is the "property" construct:
property <name>
<body>
endproperty
This can then be instantiated as:
assert property(<name>);
In the language extension ...
- 29
-1
votes
0
answers
47
views
Timing issue in systemverilog
I have the following fetch stage (for a RISC-V system) in SV
module fetch_stage (
input logic i_clk,
input logic i_reset,
mem_if.SLAVE mem_bus,
output logic [31:0] o_pc,
output logic ...
- 71
-1
votes
0
answers
109
views
Multilanguage simulation in xcelium
I have a VHDL package which I need to add to my sv testbench.
For simplicity let's say I have my testbench module, board.sv, the module I want to test, pci_target.sv, and module (package) that I use ...
- 1
-1
votes
1
answer
72
views
What's point of port to port type of connection in TLM? [closed]
In UVM TLM1, there are three main interface types:
port — the initiator of a transaction,
export — a proxy that forwards port requests to an implementation,
imp — the implementation, which contains ...
0
votes
1
answer
61
views
System verilog constraint for queues with fixed number of 6s
Can someone help me with system verilog constraint for the below requirement.1) Fixed queue size of 10 and has four 6s in it at random position.
I tried the below constraint to start with.
class ...
- 11
-1
votes
1
answer
77
views
In a System Verilog FSM can a repetitive State be converted to a Task?
I'm writing an FPGA state machine in System Verilog to read bytes from a SPI port and parse them into commands to the FPGA. The "RXSPIBITS" state is used to read SPI bytes by multiple other ...
- 9
4
votes
1
answer
105
views
How can I simulate a simple elevator FSM where it can detect overweight?
I've been doing a finite state machine of an elevator using Verilog. The elevator contains four states:
IDLE: When the elevator is stopped.
ERROR: When the elevator's weight limit is exceeded.
MOVING:...
- 71
-1
votes
1
answer
101
views
How to swap inout wires within a contained hierarchy (of which is synthesizable)?
For context, please look at my attached diagram to see what I am trying to accomplish.
Essentially, I want to swap inout wires using a contained hierarchy that will allow me to have more modular RTL ...
- 181
2
votes
1
answer
78
views
Usage of assign: when to put it in an always or not [duplicate]
I know a lot of people have asked about when to use assign inside always, but I'm wondering if you actually have to. Is it ok to have a module where you have assign statements, but they are not inside ...
- 21
1
vote
1
answer
88
views
Should UVM testbench work with pre-synthesis or post-synthesis FPGA code? [closed]
I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow.
Should I develop my ...
- 139
2
votes
2
answers
157
views
In Vivado, what is "[Synth 8-7213] Expression condition using operand 'x' does not match with the corresponding edges used in event control" error?
When I am doing some development with Verilog and Vivado, I wrote some Verilog code as follows:
module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED);
always @(posedge clk or ...
- 80