Passing array via module in verilog

Question

I have a module named dct_8p where I have an input array of 8 elements, where each element is a 4 bit number and 8 element output array each contains 5 bit number. I want to pass each 4bit number input through the module.

I was trying to read the design through design vision. It generates an error:

/Farhana/Synopsys/dct_8p.v:56: Illegal reference to memory xin. (VER-253)

I guess I am doing very silly mistakes in array declaration which I cannot get.

module dct_8p(xin,cin,add,sub,xout);
input [3:0] xin [0:7]; 
input cin; 
output [4:0] xout[0:7]; 
input add,sub; 



//layer 1 
RCA3 #(.n(4), .approx(0)) l10(.p(xin[0]),.q(xin[]),.ci(cin),.op(add),.r(xout[0]));
.... 
.. 

module RCA3(p,q,ci,op,r); 
parameter n=4; 
input[n-1:0]p,q; 
input ci,op; 
output [n:0] r; 
parameter approx=0;
....
....

2 dimensional arrays ports are not supported in Verilog; make sure you have SystemVerilog enabled. It is recommended that SystemVerilog files use the .sv instread of the .v. — Greg
– Greg, Commented Aug 24, 2015 at 22:47
I have tried .sv extension but still i am obtaining same error. I want to pass 4 bit register value in test bench script but l10 does to receive the input. — Snigdha203
– Snigdha203, Commented Aug 28, 2015 at 3:55
Try passing -sverilog to vcs compile time switch. (This is for SystemVerilog) — Vineeth VS
– Vineeth VS, Commented Aug 28, 2015 at 5:36

sharvil111 · Accepted Answer · 2015-09-30 12:43:25Z

3

I compiled your code here and it worked perfectly. I've used xin[7] as input, as you informed.

SystemVerilog allows passing Multi Dimensional arrays as input to modules. You can modify the sample code and verify that fact.

The command for execution of SystemVerilog code using synopsis-vcs is as follows:

vcs -timescale=1ns/1ns +vcs+flush+all +warn=all -sverilog -R

answered Sep 30, 2015 at 12:43

sharvil111

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