Questions tagged [hdl]
HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.
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How to test LVDS output clock on DE2-115 using ALTLVDS_TX Megafunction?
I’m trying to test the LVDS output on my Altera DE2-115 board using Quartus Prime 18.1 Lite.
My goal is just to generate and output a clock signal over an LVDS pair using the ALTLVDS_TX Megafunction.
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In HDL, why is combinatorial feedback (due to sensitivity list) a bad thing? [closed]
In one of my online lectures, it is said that the outptut should not be a part of the sensitivity list (as it would cause combinatonal feedback).
I am unable to understand why a combinational feedback ...
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SystemVerilog threads execution order
I am trying to start few threads in SystemVerilog, as can be seen in the code below:
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Using of physical FPGA for PCB prototyping
Does it make sense use a physical (real, not virtual model) FPGA while in the printed circuit board (PCB) developing cycle?
FPGA and my future PCB will have different element basis (standard cells). ...
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Vivado warning: extra semicolon in not allowed here in this dialect; use SystemVerilog mode instead [closed]
Testbench source code:
I have a testbench from another project which has the same structure, but I haven't seen this error:
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Verilog: Assignment not working as expected
I'm working on building a simple processor in Verilog. I'm now implementing the branch related instructions, but I'm observing some wrong (or at least unexpected) behavior. When I reach a branch ...
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Is there a race condition in the hardware from using a signal as both clock and reset?
What is the synthesis result on this signal used as both clock and reset?
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Using a parameter as a macro in system verilog code
Assume that I have below module definition with a parameter N:
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Whats the error?
I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct.
Someone can tell if I'm missing something, please.
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FPGA arithmetic implementation
How does an FPGA synthesis tool decide how to implement arithmetic operations on the target hardware?
For example, if I implement some integer multiplication and division operations directly in HDL ...
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D latch module in VHDL using NAND structure [closed]
What is the difference between a positive-level D latch and a negative-level D latch?
How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
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A NAND gate with propagation delay in VHDL
I want to design a NAND gate (\$t_{PLH}\$ = \$t_{PHL}\$ = 10ns) with VHDL.
\$t_{PLH}\$ = Propagation delay low to high
\$t_{PHL}\$ = Propagation delay high to low
This is first code.
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Fixed point multiplication circuit in HDL doesn't work as expected
I am implementing a fixed point multiplication circuit in SystemVerilog to multiply 2 64-bit numbers, each has 20 bits of decimal part (which remains 44 bits of integer part). The problem is the ...
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Where to register value in Verilog?
I'm looking for some help understanding a synthesis error I run into frequently with Verilog code on an FPGA platform (Lattice ECP5U).
Here's a simplified setup that produces the error. ...
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