D latch module in VHDL using NAND structure [closed]

Question

What is the difference between a positive-level D latch and a negative-level D latch?

How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for these?

Answer 1

What is the difference between a positive-level D latch and a negative-level D latch?

Go from the words: The "positive-level D latch" latches the data when the level on the control/clock input is positive. The "Negative-level …" when the level is negative.

How to create…

you use a procedural list, triggered by a sensitivity on high or low state, essentially. This is really VHDL basics, so giving you an example is of little worth.

in VHDL using NAND structure

Note that "VHDL" doesn't care about whether your logic elements is NAND, NOR, 6-bit input logic cells, or elementary school children that you told to behave in a specific way, so that question doesn't in itself make too much sense: Either your technology mapper has a logic mapping that maps to a D-Latch, or it doesn't. Note that in most things you'd define using VHDL, edge triggering is more common.