FPGA arithmetic implementation

Question

How does an FPGA synthesis tool decide how to implement arithmetic operations on the target hardware?

For example, if I implement some integer multiplication and division operations directly in HDL statements, the hardware implementation options could be:

• A LUT for all possible input combinations.
• Some multiplication or division algorithms such as Booth / Baugh-Wooley etc. using full adders.
• An ALU.

Does the synthesis tool just do the first option and generate a LUT for all input combinations unless a specific architecture is defined?

Is there any way of knowing what implementation the synthesis tool has used?

Answer 1

It's going to depend on the target FPGA part and the synthesis tools used.

With the most basic FPGAs and tools, all of your RTL code gets divided up into combinational Boolean equations and registers. All arithmetics get converted into Boolean equations. Those equations get partitioned and mapped into the LUTs for the best utilization.

As you go up the scale of increasing FPGA complexity, they start including blocks for operations like addition, multiplication, and multiply/accumulate. And they can get up to full blown ALUs. Synthesis tools will try to map your RTL to the highest level blocks available, and everything else gets mapped into LUTs.

Of course, many FPGAs now contain large CPUs, but synthesis tools are not advanced enough to map to them automatically—you must manually instantiate them.

Most vendor's synthesis tools provide reports or schematics that show how your RTL got mapped.

Answer 2

Each serious FPGA synthesis tool chain includes tools to output the resulting RTL design. The accompanied documentation lists them and their usage.

Commonly you can expect at least these two options:

1. A textual view in form of a set of VHDL sources, which contain lots of primitive components and their connections.
2. A graphical view in form of a set of schematics, which show lots of primitive components and their connections.

The set of VHDL sources is the prerequisite to test against the timing requirements.