Questions tagged [lattice]
Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.
125 questions
1
vote
1
answer
110
views
FPGA stops communicating when power cycled
I'm working with a Lattice FPGA (LCMXO2-1200HC-4TG144C) and a program that has always worked until now. This problem is driving us nuts.
Recently, I made a new PCB with a new FPGA and other components....
- 127
1
vote
1
answer
101
views
Lattice ECP5 output slew rate not in datasheet
The ECP5 sysIO datasheet mentions two programmable skew rates (FAST and SLOW) for LVTTL and LVCMOS outputs but the actual slew rate value is never given.
Has anyone measured the output signal rise ...
1
vote
1
answer
111
views
Simple PMOD connector situated upside down from what's documented on an Icestick FPGA evaluation board?
Referring to the Icestick evaluation kit for the iCE40-HX1K FPGA.
The board has a PMOD 12 pin connector. According to the board's manual, as well as various other online sources, the GND and 3.3V pins ...
- 23
2
votes
1
answer
127
views
Can I Use a Buck Converter to Step Down USB Power to 3.3V and Increase Current?
I'm a newbie in electronics and working on a project where I want to power a custom FPGA board via USB-C 2.0. The USB source provides 500mA.
I’m planning to use a buck converter to step down the 5V to ...
- 31
3
votes
1
answer
88
views
Small Resistors on Power Supplies of Lattice iCE Development Kits?
What is the function of R30 and R35 in the Lattice iCE development kits (iCE40HX-8K Breakout Board or iCEstick)? One possibility I've considered is that they help limit ramp rates or control the power-...
- 167
1
vote
1
answer
109
views
FIFO Not Storing Sequential Data Correctly in ICE40UP5K FPGA – Possible Timing Issue
A bit relevant data about the project
I'm working on a project that includes sampling a 10 MHz analogue signal at around 60 Msps on an ADS4222 (2 12 bit channels). The clock is generated using the ...
- 153
0
votes
1
answer
212
views
Lattice FPGA - RAM_DP - Write/Read Enable
In Lattice Diamond I'm using the “RAM_DP” EBR component from the IPExpress page.
The FPGA I am using is a LCMXO3LF-4300E-5MG121I.
I'm confused whether the “WE” input controls both writing/reading, or ...
- 37
0
votes
1
answer
413
views
Lattice Diamond PLL Configuration for decimal output
I have been working on a Lattice FPGA to configure a 37.125MHz output for a 24MHz input clock... but the only way I have been able to accomplish getting this is with a 5% tolerance and a big ...
- 53
1
vote
1
answer
465
views
Lattice FPGA - JTAG Programming 6Pin VS 10Pin
I'm using a Lattice MachXO3LF FPGA, specifically the LCMXO3LF-4300E-5MG121I, and I want program it using JTAG and the HW-USBN-2B programming cable from Lattice. In the Programming Cable Users Guide, ...
- 37
2
votes
1
answer
215
views
MachXO2 VHDL Internal Oscillator - "ERROR: formal nom_freq is not declared"
I am trying to run the code below, but I get an error on line generic map(NOM_FREQ => "2.56"); and I am very confused why. The error says "ERROR - ...
- 53
0
votes
1
answer
119
views
How does a Lattice MachXO3LF FPGA handle undefined IO states?
In the Lattice MachXO3LF FPGA, if an IO pin voltage is in between the thresholds for VIH min and HIL max, how does the FPGA handle this?
How does the FPGA handle if the undefined state was reached ...
- 37
2
votes
1
answer
112
views
Lattice MachXO3 FPGA VIL and VIH of Mixed Voltage I/Os
The Lattice FPGA MachXO3 sysIO User Guide, page 12, under section "7. VCCIO Requirement for I/O Standards":
it mentions that an:
input buffer set up to be a 1.2 V ratioed input can be used ...
- 37
0
votes
1
answer
145
views
Lattice MachXO3LF FPGA Internal Clock Accuracy
On the data sheet for the Lattice MachXO3 FPGA family, it shows that the internal oscillator has varying nominal frequencies with +/- 5% accuracy. Does this apply to its entire temperature range ...
- 37
3
votes
1
answer
175
views
Reset issue while issuing commands to SD card
I am busy with a project where I'm trying to make a custom flashcard for the Gameboy (for more details, refer to https://efacdev.nl/projects/ecgc). For the flashcard, I am trying to load games from an ...
- 283
1
vote
1
answer
82
views
Stateful logic synchronization clock with memory read/writes
I am working on a hobby project using Verilog and iCEstick evaluation board. I have a stateful logic (FSM) which needs to read and write to the on-chip block RAM. Now I am a little bit confused, it is ...
