Questions tagged [clock]
A digital signal that goes high and low at a specific frequency.
1,285 questions
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Output frequency variation of AD9523-1
I am working on an AD9523-1 board and from that I want to generate a 122.8800 Hz fixed output clock. The poblem is that I configured the o/p of PLL2 is exactly 122.88 I see on frequency counter it is ...
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I2S over pinheader connection for internal board to board/wire connections
Question:
Is it ok to use standard 2.54 mm pinheaders to transfer I2S signals (digital audio) from board to board or from board to wire (coax cables with UFL in the other end)?
The plan was to have ...
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How is systick interrupt set in this STM32 firmware?
I'm using STM32CubeIDE with HAL to program an STM32F3O3 MCU. In my firmware a custom function uartTimer is called inside the SysTick_Handler(which is in stm32f3xx_it.c) as:
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Spartan-3A - GCLK vs LHCLK vs RHCLK
What is the difference between the GCLK vs LHCLK vs RHCLK on a Spartan-3A FPGA? From the “Spartan-3A FPGA Family” datasheet I found the below description.
The “GCLK” global clock inputs can optionally ...
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FSM to latch first of three pulses and hold winner until reset - interview question [closed]
Interview Question:
I have a small “race” problem to implement as an FSM using D flip-flops only. There are three lanes. At the end of each lane there is a pushbutton circuit that outputs a clean one-...
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Latch based clock mux
I have been studying the clock muxed from this source:
https://vlsitutorials.com/glitch-free-clock-mux/
In this and many other websites, the clock mux is a flip-flop-based circuit. From what I ...
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According to this AppNote, I don't need to match source and load impedence. Why?
I am working on a board to distribute PPS in my house and came across this AppNote from Renesas. It shows that in a 50 ohm environment, I can just terminate to a 50 Ohm resistor, without worrying ...
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What's the difference between 'EXTRACT_ENABLE' and 'DIRECT_ENABLE'?
Both attributes are used to tell Vivado if we want to use the enable pin of a DFF. What's the difference between them? When is one more preferable than the other?
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What is "induced grounding", mentioned on 74HC595 and other datasheets?
IC devices with clock inputs require that the input signal have a rise time quick enough that the device recognizes it as only a single transition. The clock signal should avoid remaining in the 0-to-...
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Transistors: High Frequency on Collector = Parasitic Coupling to Base. Is it dangerous?
Problem:
I have a 50 MHz clock signal on a PCB trace.
That trace is going to two places: GPIO 0 on the ESP32 (where it's being consumed), and to the Collector of an NPN transistor (where it's ...
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12V to 1.5V 700mA DC converter for Quartz Clocks
Problem: I have an aftermarket (quartz) clock in my automobile. It now runs off a single AA (1.5V alkaline) battery. I wish to delete the AA battery and connect the clock directly to the OEM wiring in ...
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Shift Phase Offset of Clock using only Digital Logic? [closed]
Suppose I have 3 separate square-wave digital 5V clocks, named A, B and C. All 3 clocks are ...
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What does 'clocked out' mean?
In 7 Series FPGAs Configuration (UG470), Xilinx says,
DOUT is the data output for a serial configuration daisy-chain. DOUT is clocked out on the falling edge of CCLK.
What does it mean by 'clocked ...
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O'scope probe fixes circuit
I am building Ben Eater's 6502 computer with my own variations. The one I am currently working on is using the Versatile Interface Adapter's internal shift register to shift in keyboard input, thereby ...
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D Flip-Flop and Clock in Sigma-Delta Modulation
Image source
Hi everyone,
I’m trying to understand how sigma-delta modulation works, but I’m really struggling with the role of D flip-flop and clock in the process.
I’ve read several references, but ...
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