Questions tagged [zynq]
Zynq is a range of programmable SoCs from Xilinx, that integrate an ARM-based processor and an FPGA fabric.
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Ethernet link ss only up with 10Mbps, No 100 or 1000Mbps even in forced condition
We are using Marvell 88E1512 with Xilinx ZU2CG SOC for 1000Mbps ethernet.
Currently we are facing issue with ethernet link.
Attached the schematics for your reference.
The system description is below....
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Series termination placement next to receiver
I have series termination resistors very close to the receiver, I have realized that they must be next to the driver (can't be moved since Im using a SOM).
The parallel HDMI input signals that go into ...
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LVDS input termination in Vivado Pin Planner
I'm trying to confirm a Zynq XC7C030 SOM is suitable for data acquisition from an LVDS (1.8V) ADC eval board. The pin assignments are out of my control, but they map to bank 35, which is an HP bank ...
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Can I program ZCU106 (Zynq Ultrascale+ MPSoC) with Simulink Embedded Coder without Vitis?
I’m new to working with the ZCU106 (Zynq Ultrascale+ MPSoC) evaluation board and am trying to write a simple "Hello World" program (e.g., toggling a user LED) using Simulink Embedded Coder ...
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Zynq SoC Schematic review
I am kind of finishing up hardware design based on AMD Zynq 7010 SoC which has different peripherals. This is the most complex design that I have done in my past and I wanted to get some sort of ...
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microSD card different footprint
I am trying to integrate microSD card on my SoC design. I see these two different type of footprints. I believe that functionalities are the same but what's the reason that these two footprints are ...
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Programming Xilinx board using FT232 breakout board
Im trying to program my board via the FT232 because I'll be using that chip in my own development board around the same SOM my dev board uses (MYD-C7Z020 V2). My board doesn't show up in HW manager. ...
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AMD Zynq SoC with HDMI
I am relatively new to FPGA board design.
I am interfacing HDMI TX to FPGA (Zynq 7010 SoC) as shown below. My understanding is that Zynq supports TMDS signals so I can use any of High-Range I/O in PL ...
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Understanding MIPI CSI-2 signals level
I am referencing an existing design that connects this camera through MIPI CSI-2 interface. I could just take this pinout and have it implemented on my custom board using same SoC used in the ...
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MIPI CSI-2 Camera schematic
I am trying to design schematic and PCB for different high-speed peripherals including CSI-2 camera. I don't have previous experience designing specifically CSI-2 interface but I see open sourced ...
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Efuse programing using XilSKey lib, Zynq UltraScale+
I'm working with Zynq UltraScale+ and using the XilSKey library for EFUSE programming over JTAG. I came across the JtagReadUltra function, which prepares a buffer (<...
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Where is XPAR_AXI_GPIO_0_DEVICE_ID defined in xparameters.h in Vivado/Vitis?
Example code for reading/writing AXI GPIO IP modules in AMD Zynq Vivado/Vitis projects
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Frequency range for ESR of decoupling capacitor used in Xilinx FPGA
I am trying to do own PCB design based on Xilinx FPGA Zynq 7010. Their application note (UG933) provides recommended decoupling capacitor values with its ESR range, but they do not specific the ...
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How to connect switches and LEDS to Zynq FPGA in Vivado
(new a FPGA / Vivado development) How do I 'connect' DIP switches, or LEDs on a (Zybo Z7) FPGA development board to 'devices' (ip blocks) I have in the Vivado PL 'diagram'?
In the Vivado Diagram I ...
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Interfacing high-speed ADC with ZYNQ 7020
I need to interface a high-speed ADC (100 Msps or higher data rate) with a ZYNQ 7020 core board, which has limited number of pins available to use (100 pins). I need to sample a 30 MHz signal with my ...
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