I am currently in progress designing SoC based on AMD Zynq7010 with two DDR3 memory (MT41K256M16TW-107IT:P). I am utilizing fly by routing. Upper memory is 2nd DDR3 memory and lower memory is 1st DDR3 memory. I am planning to run memory with clock frequency of 533MHz. Please see below image for routing.
I have two groups of signals that are matching delays for the relevant group (I am only showing one of address signal in the picture as an example, but I matched delays all address, ctrl and clocks). One is from controller to 1st memory and other is controller to 2nd memory.
For example,
A -> B -> D is 500 ps
A -> B -> C is 600 ps
From my research and comments from here, I do not need to worry about delay matching between memories as long as I match from controller to each memories.
My question is, do I need to worry about stub created between the via and 1st DDR3 memory (B -> C)? This via is shared for two path, one is going to 2nd memory and other is 1st memory (A,B,D and A,B,C as descried above). I didn’t consider this as an extra stub but someone from my college pointed out that this could be an extra stub and causes whole signal integrity issue.. I have quite a few of these stubs with max length of 13mm. I could not terminate vias near the DDR3 memory due to how it's routed so have some length of stubs.. I didn't want to use via-in pad as it adds cost of manufacturing. I have not thought bout potential SI issue that could be caused by these stubs. I know that I need to simulate at the end of day but I don't have access to those tools yet. I am still in school and trying to learn as much as I can online.. I am not intending to design this board to meet EMI criteria. Just wanted a working board for now.
Thank you!
