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I want to take in a parameter and assign a number of zeroes equal to the paramter to a constant, and use this constant for comparison. how do I do it ?

For example, say parameter is 3, I want to create a constant

n=3'b000;

and use this n in another statement. Only thing is, I don't know n. How do i initialize 'n' zeroes and to what verilog data type do I assign it to ?

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2 Answers 2

34

Your looking for the replication operator. The syntax is {replication_constant{value}}.

An example of creating a bus of size WIDTH to all zeros.

parameter WIDTH = 3;
wire [WIDTH-1:0] n = {WIDTH{1'b0}};

For full description of the replication operator, see IEEE std 1800-2012 § 11.4.12.1 "Replication operator"

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5 Comments

You can also skip the replication and just do wire [WIDTH-1:0] n = '0; to assign every bit to 0.
@nguthrie, the fill zero ('0) is for SystemVerilog, the SO's question is for Verilog.
you cited the 1800-2012 standard, so I figured it was fair game. In my view SV is just the latest version of Verilog so people might as well hear about the SV syntax even if they didn't tag their question with it.
supposing it was 1 followed by n zeroes ?
@Floose In Verilog, just replace the 1'b0 with whatever value you want, such as 1'b1 for all 1s. SV has fill values '0,'1,'x,'z (case insensitive).
17

To expand Gregs answer and answer what if you wanted 1 then all 0's.

Use a mixture of concatenation {a,b} and replication {width{c}}:

wire [WIDTH-1:0] n = { 1'b1, {WIDTH-1{1'b0}} } ;

While the '0 or '1 syntax is in use in SystemVerilog 'b0 for width matching is valid in older Verilog. In verilog-95 it would only width match upto 32 bits but that has since been rectified.

Example defining the reset values on flip-flops :

reg [7:0] a;
always @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    a <= 'b0 ;
 ...

2 Comments

Is there a way to assign an arbitrary value, like WIDTH'd345?
@Nazar No, although you could try use a global tick-define `define WIDTH 4, the use `WIDTH'd345

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