Using parameter for continuous assignment in verilog?

Question

Can you use a parameter value for assignment in verilog? Can I somehow define the width of a parameter variable?

Ex:

module mymodule #(parameter type =2)
    (...
    output [(3+type)-1:0] out);
    wire [2:0] rate;
    ...
    assign out = {rate, {1'b0{type}} };
endmodule

Lets just say type=2. Then I would want out to be of bit-length 5. rate is still of bit-length 3 (lets just say it is 3'b100), when I assign out I want it to be 100 000.

Similarly if type=6. Then I would want out to be of bit-length 9. rate is still of bit-length 3 (again lets say its 3'b100), when I assign out I want it to be 100 000000.

I don't get any syntax errors but when I try to simulate it I get: "error: Concatenation operand "type" has indefinite width"

How would you guys approach a design problem like this one?

Tim · Accepted Answer · 2013-02-01 01:04:32Z

4

You have the repetition operator backward. Should be

{type{1'b0}}, not {1'b0{type}}

I'm surprised you don't see any syntax error from that.

answered Feb 1, 2013 at 1:04

Tim

36k11 gold badges99 silver badges124 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

Using parameter for continuous assignment in verilog?

1 Answer 1

Comments

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Related