Verilog: "... is not a constant"

Question

I have three wires created like this:

wire [11:0] magnitude;
wire [3:0] bitsEnd;
wire [3:0] leadingBits;

All of them are assigned some expression using combinational logic. The following code works fine:

assign leadingBits[3] = magnitude[bitsEnd + 3];
assign leadingBits[2] = magnitude[bitsEnd + 2];
assign leadingBits[1] = magnitude[bitsEnd + 1];
assign leadingBits[0] = magnitude[bitsEnd + 0];

However, the following (seemingly equivalent) code gives the error bitsEnd is not a constant:

assign leadingBits[3:0] = magnitude[bitsEnd + 3:bitsEnd];

Can I not use shorthand for this assignment? Why would this error be raised in the second case but not the first?

Community · Accepted Answer · 2017-05-23 11:44:40Z

7

In Verilog you can't use a variable (i.e. bitsEnd) as the end of range. You can use +:/-: operator to solve your issue:

assign leadingBits = magnitude[bitsEnd+3 -: 4];

In the first case you only calculate single index (it's not a range). That's why the compiler is not complaining about it.

edited May 23, 2017 at 11:44

CommunityBot

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answered Apr 23, 2015 at 7:46

Qiu

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