Change parameter value in Verilog

Question

I would like to change parameter value in Verilog depending on 3 bit digital input pin value. Here is a sample from my verilog code.

paramter real C_IP=0;

 always @ (reg_DACIP)
   begin
     case (reg_DACIP)
      3'b000 : C_IP = 0.8;
      3'b001 : C_IP = 0.6;
      3'b010 : C_IP = 0.4;
      3'b011 : C_IP = 0.2;
      3'b100 : C_IP = 0.0;
      3'b101 : C_IP = -0.2;
      3'b110 : C_IP = -0.4;
      3'b111 : C_IP = -0.6;
    endcase
end

When I compile I get this error:

ncvlog: *E,PANOTL: A parameter is not a legal lvalue [3.10(IEEE)].
      3'b001 : C_IP = 0.6;

I understand Verilog parameters are for constants, and therefore can not be changed during simulation. However what would be the best workaround over this problem?

Greg · Accepted Answer · 2016-07-12 19:36:03Z

Parameters must be a constant, there is no way around it. A parameter can be a function of other parameters. A parameter can be changed to another constant at compile/elaboration time via #() in module instanciation or defpram (note defpram is planned for depreciation). A parameter will update to its new value if the paramter(s) it is derived from is changed during compile/elaboration. Examples of parameters derived from another parameter:

// nested conditional statement
parameter real C_I P = PARAM_DACIP==3'b000 ? 0.8 :
                       PARAM_DACIP==3'b001 ? 0.6 :
                       PARAM_DACIP==3'b010 ? 0.4 :
                       PARAM_DACIP==3'b011 ? 0.2 :
                       PARAM_DACIP==3'b100 ? 0.0 :
                       PARAM_DACIP==3'b101 ? -0.2 :
                       PARAM_DACIP==3'b110 ? -0.4 : -0.6;

// simple expression
parameter real C_IP = 0.2*(3'b100-PARAM_DACIP);

// pure static function (i.e. output only determined from input)
// Note: not all simulators/synthesizers support this
function real calc_C_IP( input [2:0] DACIP);
begin
  case (DACIP)
    3'b000 : calc_C_IP = 0.8;
    3'b001 : calc_C_IP = 0.6;
    3'b010 : calc_C_IP = 0.4;
    3'b011 : calc_C_IP = 0.2;
    3'b100 : calc_C_IP = 0.0;
    3'b101 : calc_C_IP = -0.2;
    3'b110 : calc_C_IP = -0.4;
    3'b111 : calc_C_IP = -0.6;
  endcase
end 
endfunction
parameter real C_IP = calc_C_IP(PARAM_DACIP);

if reg_DACIP must be a register, then C_IP cannot be a parameter. You can make it a regular real

FYI: real is not synthesizable

Thanks Greg. In your function example, what is PARAM_DACIP? DACIP is 3 bit logic input pin in my code. How do I pass it to calc_C_IP function?
Also in your fist nested conditional statement solution, what is PARAM_DACIP? How can I relate it to 3 bit DACIP input pin?
@Sandeep, in your original code you used reg_DACIP which I assumed was a reg type, I changed reg_ to PARAM_ in my example to sugest it is a parameter and not a register. you an assume that PARAM_DACIP is defined as parameter [2:0] PARAM_DACIP = 3'b100; (or some other value)

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