I want to use a 2D array in a Verilog testbench. I tried it this way:
module tb;
reg [7:0] DataToSend [0:7] = {8'h01, 8'h10, 8'h22, 8'h32, 8'h55, 8'hAA, 8'hAB, 8'h88};
endmodule
But this gives me the following error:
cannot assign a packed type to an unpacked type
What's the correct way? And is it that it doesn't work in Verilog but would work in SystemVerilog?
The syntax in your code is only supported by SystemVerilog (IEEE Std 1800). It is not supported by Verilog (IEEE Std 1364).
In Verilog 1364-2005, section 4.9.3 Memories (emphasis added):
An n-bit reg can be assigned a value in a single assignment, but a complete memory cannot. To assign a value to a memory word, an index shall be specified.
Most simulators are capable of understanding SystemVerilog (SV) syntax, but many do not have the features enabled by default. You likely need to enable the SV features when you run a simulation. Refer to your simulator documentation. This is the simplest way to avoid the syntax error.
Otherwise, if you are stuck with Verilog for some reason, then there are ways to avoid the syntax error. For example:
reg [7:0] DataToSend [0:7];
initial begin
DataToSend[0] = 8'h01;
DataToSend[1] = 8'h10;
// etc.
DataToSend[7] = 8'h88;
end