The error "requires SystemVerilog extensions" while declaring an error

What's wrong with the following code? The array "FIFO" is declared correctly, but an error appears. Can you please help how to fix this?

module fifo(
    input clk, 
    input [7:0]data_in ,
    output reg [7:0] FIFO [0:8]
);

integer i;
always@(posedge clk) begin
       for(i = 8; i > 0; i=i-1) begin
          FIFO[i] <= FIFO[i-1];
       end
       FIFO[0] <= data_in;
end
endmodule

Error (10773): Verilog HDL error at fifo.v(29): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions