SystemVerilog: virtual modules verse virtual interfaces

Question

I know that SystemVerilog allows you to save a reference to an interface in a SystemVerilog class by declaring it as "virtual". Bus, is it also possible to declare a module as "virtual" in order to save a reference to a module in a SystemVerilog class? Example:

    `timescale 1 ns / 10 ps

    // Verilog-95 style BFM (with verilog 2001 style ports)
    module BFM1(
        input  wire        clk,
        output reg [15:0]  data
    );

        task write(input [15:0] data1);
            data = data1;
            @(posedge clk); 
            #1;
        endtask;

    endmodule

    class MyClass

        //"Virtual module" (instead of a "virtual interface")
        virtual BFM1 vBFM1;

        function new(virtual BFM1 vvBFM1);
            // save virtual module reference
            vBFM1 = vvBFM1;
        endfunction

        function write(input [15:0] data);
            vBFM.write(data);
        endfunction
    endclass

    // Testbench top-level
    module top;
        reg        clk;
        reg [15:0] data;

        initial begin
            clk = 0;
            forever #5 !clk = clk; 
        end

        BFM1 BFM1(
            .clk  (clk),
            .data (data)
        );

        DUT DUT(
            .clk  (clk), 
            .data (data)
        );

        initial begin

            //Verilog-95 Style BFM call
            BFM1.write(16'h12340);

            // SystemVerilog Class style
            MyClass MyClass1 = new(BFM1);

            MyClass.write(16'hDEAD);
            MyClass.write(16'hBEEF);

            $finish;
        end
    endmodule

    // Design under Test
    module DUT(
        input wire        clk,
        input wire [15:0] data
    );
        //insert design under test logic
    endmodule

I was just curious, if I could dispense with the formality of using a SystemVerilog interfaces, and just use an old verilog-95 Style BFM's from a SystemVerilog Class?

I just think the old style BFM's would work better in a SystemVerilog testbench if your DUT is in VHDL, since VHDL doesn't have SystemVerilog interfaces. Its kind of redundant to create unnecessary interfaces and packages just to plug a SystemVerilog testbench into a VHDL DUT that doesn't use them.

Answer 1

The direct answer to your question is no, SystemVerilog has limited constructs that you can get handles to (interfaces, classes, and events). The biggest problem is that modules are not like data types that have to be defined before being referenced. It's very difficult and non-optimal creating a reference to an identifier when you don't know its type.

The original SystemVerilog interface specification was much simpler than it is today. Its features have grown to look more like a module, but still more restrictive.

However, alternatives to virtual interfaces, especially when communicating with legacy Verilog BFMs is a frequently discussed topic. link1 link2 link3

Answer 2

    `timescale 1 ns / 10 ps

    // The best why to solve this problem since the SystemVerilog
    //  language standard people did't give us a handle to a module
    //  is to create a define that points to full hierarchical path to
    //  the verilog module. Example:

    `define   DEF_BFM1   $root.top.BFM1

    // Verilog-95 style BFM (with verilog 2001 style ports)
    module BFM1(
        input  wire        clk,
        output reg [15:0]  data
    );

        task write(input [15:0] data1);
            data = data1;
            @(posedge clk); 
            #1;
        endtask;

    endmodule

    class MyClass

        function write(input [15:0] data);
            `DEF_BFM1.write(data);
        endfunction
    endclass

    // Testbench top-level
    module top;
        reg        clk;
        reg [15:0] data;

        initial begin
            clk = 0;
            forever #5 !clk = clk; 
        end

        BFM1 BFM1(
            .clk  (clk),
            .data (data)
        );

        DUT DUT(
            .clk  (clk), 
            .data (data)
        );

        initial begin

            //Verilog-95 Style BFM call
            `DEF_BFM1.write(16'h12340);

            // SystemVerilog Class style
            MyClass MyClass1 = new();

            MyClass.write(16'hDEAD);
            MyClass.write(16'hBEEF);

            $finish;
        end
    endmodule

    // Design under Test
    module DUT(
        input wire        clk,
        input wire [15:0] data
    );
        //insert design under test logic
    endmodule