Using packages with classes and virtual interfaces

Question

I'm a relative newbie to SystemVerilog.

I have a package with class A defined in it. This class uses a virtual interface, since it's a driver (BFM) in a testbench. I'm using a package so I can use the same BFM in other designs.

In my testbench, I import the A class and pass to it an instance of the virtual interface. However, when a task in the class tries to assign a value to a signal in the interface, I'm getting a compilation error.

What am I doing wrong? How can one package a BFM with a virtual interface?

Answer 1

SystemVerilog packages cannot include interfaces within the actual package. So your interface needs to be compiled along with you package source. The classes you define will reside in the package while the interface definition resides in the global scope where modules live.

Classes within packages can make references to virtual interfaces, but you need to make sure the interface is compiled and visible, apart from the package source.

Answer 2

Strictly according to the spec, I don't think this is possible since it adds an implicit external dependency:

Items within packages are generally type definitions, tasks, and functions. Items within packages shall not have hierarchical references to identifiers except those created within the package or made visible by import of another package. A package shall not refer to items defined in the compilation unit scope.

It doesn't say anything about the design element namespace, which is where interface declarations live, but accessing any member of an interface requires a hierarchical reference.

You should consider packages to be completely self-contained, other than pre-processor directives and import.

Answer 3

Generally the class declaration not present before its usage is resolved with the help of systemverilog typedef definition. For example "Class A uses Class B" and "Class B uses class A" then typedef is used to resolve the stalemate.

Now when you bring in the package with the above scenario then one needs to ensure both Class A and Class B have to be in same package. If they are not then the compile wont go through.

The reason being the SystemVerilog parser will need the definition of the classes indicated with the typedef at the end of the package parsing. This fails.

This issue needs to watched out that "typedef does not apply across package".