systemVerilog signed doesn't work correctly

Question

I have the following function:

   function tx_upconv_out_transaction predict(tx_upconv_in_transaction in_trx);
      tx_upconv_out_transaction predicted = tx_upconv_out_transaction::type_id::create("predicted");
      //-------golden model-----
//      predicted.y = (in_trx.xi * in_trx.cos - in_trx.xq * in_trx.sin)/ (2 ** 17);
      $display(" xi = %d, cos = %d xq = %d sin = %d", $signed(in_trx.xi),$signed(in_trx.cos),$signed(in_trx.xq),$signed(in_trx.sin) );
      predicted.y = ($signed(in_trx.xi) * $signed(in_trx.cos) - $signed(in_trx.xq) * $signed(in_trx.sin))/ (131072);      
      return predicted;
   endfunction: predict 

Where: The field in in_trx are defined by:

   bit [15:0]  xi;
   bit [15:0]  xq;
   bit [15:0]  sin;
   bit [15:0]  cos;  

For the input:

xi, qq = fffa (hex)
sin = 0
cos = 7ffe (hex)

The output (display) is:

xi =     -6, cos =  32766 xq =     -6 sin =      0

Where it should be:

 xi =     -6, cos =  -2 xq =     -6 sin =      0

Answer 1

You can declare your vectors to signed and unsigned (default). Eg.:

logic signed [3:0] signed_reg; // a 4-bit vector in range -8 to 7

From now you you will not need $signed systemcalls. Also if you are using 16 bit 2-state variables you should consider the built in shortint type that is a 2-state data type, 16-bit signed integer.