Error in program block and Systemverilog testbench:

I have pasted my verilog design, systemverilog testbench and errors. You can paste them on edaplayground.com and simulate them. Please give me suggestions to remove errors. I think problem is in program block, but it doesn't seem to be problematic to me.

//########################## D E S I G N ##########################################
`timescale 1 ns / 1 ns

module addsub_cy (
   opa_i,
   opb_i,
   addsub_i,
   cy_i,
   cy_o,
   rslt_o);

parameter DWIDTH = 4;

input   [DWIDTH - 1:0] opa_i; 
input   [DWIDTH - 1:0] opb_i; 
input   addsub_i;  // It will decide addition or subtracton. 1 for addition and 0 for     subtraction. 
input   cy_i; // carry_input
output   cy_o; 
output   [DWIDTH - 1:0] rslt_o; 


// --
reg     cy_o; 
reg     [DWIDTH - 1:0] rslt_o; 
reg     [DWIDTH:0]  p_addsub_v_a; //temporary register to store input a           Extra     one bit will be used to prepend carry bit.
reg     [DWIDTH:0]  p_addsub_v_b; //temporary register to store input b
reg     [DWIDTH + 1:0]  p_addsub_v_result; //temporary register to store result. 

//  process p_addsub


always @(opa_i or opb_i or addsub_i or cy_i)
   begin : p_addsub
   p_addsub_v_a[DWIDTH:1] = opa_i;   
   p_addsub_v_b[DWIDTH:1] = opb_i;   
   if (addsub_i === 1'b 1)
      begin
      p_addsub_v_a[0] = 1'b 1;   
      p_addsub_v_b[0] = cy_i;   
      p_addsub_v_result = p_addsub_v_a + p_addsub_v_b;   
      end
   else
      begin
      p_addsub_v_a[0] = 1'b 0;   
      p_addsub_v_b[0] = cy_i;   
      p_addsub_v_result = p_addsub_v_a - p_addsub_v_b;   
      end
   cy_o <= p_addsub_v_result[DWIDTH + 1];   
   rslt_o <= p_addsub_v_result[DWIDTH:1];   
   end


//  purpose: Simple adder/subtractor with carry/borrow
//  type   : combinational
//  inputs : opa_i, opb_i, addsub_i
//  outputs: cy_o, rslt_o

// --

endmodule // module addsub_cy
//###############################################################################


//########################## T E S T B E N C H     ##########################################
`timescale 1 ns / 1 ns 
module addsub_cy_tb ();

parameter DWIDTH = 4;

reg   [DWIDTH - 1:0] opa_i; 
reg   [DWIDTH - 1:0] opb_i; 
reg   addsub_i; 
reg   cy_i; 
wire   cy_o; 
wire   [DWIDTH - 1:0] rslt_o; 
//int count = 100;

addsub_cy u0 (   
   .opa_i(opa_i),
   .opb_i(opb_i),
   .addsub_i(addsub_i),
   .cy_i(cy_i),
   .cy_o(cy_o),
   .rslt_o(rslt_o)
   );

  //Instantiating program block
  test test_instance (addsub_i, opa_i, opb_i, cy_o, rslt_o);

endmodule

  parameter DWIDTH = 4;

program test(input logic addsub_i, input logic [DWIDTH - 1:0] opa_i, input logic [DWIDTH     - 1:0] opb_i, output wire cy_o, output wire [DWIDTH - 1:0] rslt_o ); 
  //ADD CARRY INPUT cy_i

  initial begin
    opa_i = 4'h0;
    opb_i = 4'h5;
    //static int count = 100;

    $display ("ADD=1/SUB=0 INPUT_A INPUT_B CARRY_OUT RESULT");
    //end  
    //initial begin
      repeat (100) begin 
        #5 opa_i = opa_i + 10;
            opb_i = opb_i + 5;
        $display ("%t %b \t %b \t %b \t %b \t %b \t %b", $time, addsub_i, opa_i, opb_i,     cy_o, rslt_o); 
        end 
    end

endprogram

//#######################################################################################