SystemVerilog Parameters with defined width

Question

I have the following VHDL code that defines a constant of particular width.

constant WIDTH : natural := 16
constant X : std_logic_vector(WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(16#0#, WIDTH));

How do I define something like this in SystemVerilog?

I would assume that something like this would correspond to

parameter WIDTH = 16
parameter X = WIDTH'd1231413412

But this doesn't seem to work with my Verilog compiler

Answer 1

It Verilog, it's rare that you need to specify the width of an unsigned constant. But if you did need to, it would be:

parameter WIDTH = 16
parameter bit [WIDTH-1:0] X = 'd1231413412

Note that once you define a parameter with a data type, you can only override its value, not its type.

Answer 2

It should be something like the following:

parameter WIDTH = 16;
parameter [WIDTH-1:0] X = 0;

It will work with SystemVerilog (IEEE1800) and Verilog since 2001 (IEEE1364-2001). If you are stuck with an archaic simulator that only supports Verilog 1995 (IEEE1364-1995), it will not work.