How to initialize parameterized array parameter using loop/generate in verilog?

Question

I want to initialize a parameterized array parameter as follow:

parameter n = 4;
parameter [(log2(n)-1):0] state [(n-1):0] = '{2'h3, 2'h2, 2'h1, 2'h0}; // for n=4

This assignment works fine if n=4. When n=8, it should initialize as

{3'h7, 3'h6, 3'h5, 3'h4, 3'h3, 3'h2, 3'h1, 3'h0}

I want to initialize it like this:

for(i=0,i<n,i=i+1)
    state[i] = i;

Now what should I use to do this initialization? Can I do it with generate? Here log2 is a function.

Answer 1

First off, you are using SystemVerilog, the super-set and successor of Verilog. Verilog does not support arrayed parameters (vectors are okay) and Verilog cannot assign a whole unpacked array (the '{} is SystemVerilog).

With SystemVerilog you can auto scale the values of STATE with the following:

parameter N = 4;
parameter [(log2(N)-1):0] STATE [N] = state_val();

typedef logic [(log2(N)-1):0] state_t [N];
function state_t state_val();
  for(int i=0; i<N; i++)
    state_value[i] = i;
endfunction : state_val

_{Note: Most coding style guidelines recommend using uppercase for parameters and lowercase for variables; this allows easier readability. This is why I changed n and state to N and STATE in my answer.}