How do you initialize a parameter array in Verilog

Question

This gives me an error saying that I can't assign a packed type to an unpacked type. I agree that the right side is an array of packed types, but why is the left side of the expression an unpacked type?

parameter [7:0] lsfr_taps [0 : 7]   = {8'd9, 8'd5, 8'd3, 8'h21, 8'd9, 8'd9, 8'd5, 8'd9};

Regardless the more important question is how do I inialize a two-dimensional array of multi-bit parameters in Verilog?

0xMB · Accepted Answer · 2014-09-22 19:48:47Z

5

Your initialisation is fine. You just need to add a ' before {:

parameter [7:0] lsfr_taps [0 : 7]   = '{8'd9, 8'd5, 8'd3, 8'h21, 8'd9, 8'd9, 8'd5, 8'd9};

answered Sep 22, 2014 at 19:48

0xMB

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3 Comments

James Joshua Street Over a year ago

what does the ' mean? also, does modelsim not support displaying two dimensional signals? it seems like it compiled fine, but I can't display it in modelsim

0xMB Over a year ago

The apostrophe is used in array literals. I don't know if Modelsim supports 2D arrays for Verilog. I normally use ISim and VHDL.

Prashant Over a year ago

If using Cadence NCVerilog for simulations, you will need to include the +sv switch when running the simulator from the command line. This is to treat the files containing the parameter definitions as SystemVerilog files

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How do you initialize a parameter array in Verilog

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