I know VHDL, and just learning verilog. I'm trying to do a simple assignment with bit shift, and I get undefined 'X' in the result. I don't understand why. This is in simulation with Xilinx ISim software.
This assignment:
assign dout = $signed(data_out >>> shift_bits);
Results in 'X' wherever a '1' should be. For example, if data_out = '00001100', and shift_bits = 1, dout will = '00000XX0'.
Below is the module definition and the assignment operation:
module SensorINV(
input clk,
input [23:0] din,
input idv,
input [4:0] shift_bits,
output [23:0] dout,
output reg odv
);
reg [47:0] data_out = 0; // initialize the output
assign dout = $signed(data_out >>> shift_bits);
// assign dout = data_out[44:21]; // this didn't work either
reg [1:0] state = 0;
always @(posedge clk) begin
case (state)
0 : begin // waiting for new data
...
end
1 : begin
...
data_out <= data_out + temp1_w;
state <= 2;
end
2 : begin
...
state <= 0;
end
default : state <= 0;
endcase
end
assign dout = $signed(data_out >>> shift_bits)[UB:LB]. Also why is data_out a reg instead of a wire? Is there a synchronous block you're not showing us?reg [47:0] data_out = 0;line, which is setting up a continuous assign fordata_outto value48'd0. As such, whenever you try to assign a value of 1 to any bits ofdata_out, you get1'bxinstead. Try removing the= 0;part and see if you code works now.regit should be an initialization. If it were a net, it would be treated as a continuous assignment (iewire [47:0] data_out = 0would be a continuous assignment). I think its possible this tool is doing that even though I think you are right that it shouldnt be. I wasnt able to find what the LRM says about variable types being set at declaration so Im not 100% sure on what the behavior ofreg [47:0] data_out = 0;is strictly defined as. Still worth a short removing the initialization and seeing what happens for the simulator.