Verilog getting 'x' as an output instead of '0' and '1'

I am trying to create a four element direct mapped cache with four bit memory address. Program is running completely fine no compilation error but suddenly in output, I am getting 'x' just for the first statement. After that I don't see it anywhere else. Any help would be appreciated. Here is the code

module cache_memory_direct_mapped(input clk,
                        input reset,
                        input [3:0]read_addr,
                        output reg hit,
                        output reg miss,
                        output reg [7:0]hit_count,
                        output reg [7:0]miss_count);
reg [1:0]c1[3:0];
initial 
begin
 hit_count =8'h00; 
 miss_count = 8'h00;
end 
            

always @(posedge clk, posedge reset)                        
 begin
   if(reset)
      begin
       c1[0] <= 2'hx;
       c1[1] <= 2'hx;
       c1[2] <= 2'hx;
       c1[3] <= 2'hx;
      end   
    else  
begin
  if(read_addr[3:2] == c1[0] || read_addr[3:2] == c1[1] || read_addr[3:2] == c1[2] || read_addr[3:2] ==     c1[3])
   begin
   hit <= 1;
   hit_count <= hit_count + 1;
   miss <= 0;
   end
 else
  begin
  hit <= 0;
  miss <= 1;
   miss_count <= miss_count + 1;
    if(read_addr[1:0] == 2'b0 )
        c1[0] <= read_addr[3:2];
    else if(read_addr[1:0] == 2'b1 )
      c1[1] <= read_addr[3:2];  
    else if(read_addr[1:0] == 2'b10 )
      c1[2] <= read_addr[3:2];        
    else if(read_addr[1:0] == 2'b11 )
      c1[3] <= read_addr[3:2];  
 end
 end
 end
endmodule

module Tb_direct_mapped;

// Inputs
reg clk;
reg reset;
reg [3:0] read_addr;

// Outputs
wire hit;
wire miss;
wire [7:0]hit_count;
wire [7:0]miss_count;

integer data_file ; // file handler
integer scan_file ; // file handler
reg [4:0]captured_data;

// Instantiate the Unit Under Test (UUT)
cache_memory_direct_mapped uut (
    .clk(clk), 
    .reset(reset), 
    .read_addr(read_addr), 
    .hit(hit), 
    .miss(miss),
    .hit_count(hit_count),
    .miss_count(miss_count)
);

initial begin
    // Initialize Inputs
    clk = 0;
    reset = 0;
    data_file = $fopen("data_file.txt", "r");
end

always
#10 clk= ~clk;


always @(posedge clk) begin
scan_file = $fscanf(data_file, "%h\n", captured_data);
if (!$feof(data_file)) begin
read_addr <= captured_data;
$display(hit);
//$display(hit_count);
end
else
$finish; 
end

  
endmodule

And here is the picture of the output