Why is there no assign statement in this Verilog function?

Question

Coming from a C++ background I'm starting to learn Verilog. This code describes four inputs going into two AND gates. The outputs from those two AND gates go into an OR gate. The output from the OR gate is the final output.

// a user-defined AND gate
module my_and2 (in, out);
input [1:0] in;
output out;
assign out = in[1]&in[0];
endmodule

// a user-defined OR gate
module my_or2 (in, out);
input [1:0] in;
output out;
assign out = in[1]|in[0];
endmodule

// the AND-OR logic built on top of the user-defined AND and OR gates
module and_or (in_top, out_top);
input [3:0] in_top;
output out_top;
wire [1:0] sig;
// instantiate the gate-level modules
my_and2 U1 (.in(in_top[3:2]),.out(sig[1]));
my_and2 U2 (.in(in_top[1:0]),.out(sig[0]));
my_or2 U3 (.in(sig),.out(out_top));
endmodule

The first two modules make sense to me. However, the last one doesn't. The first two modules have an assign statement at the end to set the value for the output variable. However, the last one doesn't. Why is that?

Marty · Accepted Answer · 2011-02-26 00:16:57Z

Verilog is 'event driven'. When writing verilog, think in terms of sensitivity lists.

In your example of the AND gate, you've the expression assign out = in[1]&in[0];. Your expression is said to be sensitive to in[0] and in[1]. This means that any time in[0] or in[1] change, the expression will be recomputed, and the value of out will be updated.

So in your toplevel module and_or, you're basically building a big tree of expressions that are sensitive to the outputs of the preceding expressions. This tree is, of course, built using the module connections. So a change in the value of one of the inputs to this toplevel module will ripple through all expressions in its 'logic cone'.

To drive the inputs you'll need higher level testbench module driving signals into your and_or module. This will supply inputs spaced out in time which will trigger the expressions in and below and_or. If not, your sim will have no events, so no expressions will trigger and the sim will time-out at 0ps because it is 'event starved'.

PS: for your AND gate expression, assign out = &in; will work too... (reduction AND operator)

user597225 · Accepted Answer · 2011-02-25 21:28:22Z

2

out_top is driven by the U3 instance output.

answered Feb 25, 2011 at 21:28

user597225

2 Comments

node ninja Over a year ago

So instantiating a module automatically runs it?

user597225 Over a year ago

Actually, nothing is really 'run' in that code as it doesn't contain any procedural statements. It is a structural description showing connectivity. Of course the simulator will execute code to effect the signal changes, but these details aren't all that relevant to modeling this circuit.

Noobification · Accepted Answer · 2014-10-26 01:27:00Z

To put things simply, I like to think instantiation as just connecting wires.

Modules are blocks of digital circuits. You AND and OR gate modules are where magic happens. You already understand that part. By instantiating those modules, it's like you're connecting the input wires of your top level module with inputs of two blocks AND module. Then taking the outputs of them and taping them to the input wire sticking out of your OR block. And finally you're connecting the output of OR block to the output signal wire of top level.

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