How to pass parameters to a verilog module when performing synthesis?

Question

I have a parameterized verilog module with a bitwidth that is variable depending on the value given in `define WIDTH.

However, I would like to be able to somehow change the value of WIDTH by passing in a parameter during synthesis using design compiler.

I was wondering if there is a way to do this?

For instance, I'd like to be able to write the following for my input file for design compiler:

analyze -format sverilog -define WIDTH 10 myverilogfile.v

That probably depends on your design compiler, refer to the user manual first. One idea, if that functionality isn't built into the compiler, is to write a small script to substitute a keyword with a value, then run the analyze function. — N8TRO
– N8TRO, Commented Mar 29, 2015 at 3:42

Morgan · Accepted Answer · 2015-03-30 07:23:46Z

4

For Design Compiler the format is:

analyze -format sverilog -define WIDTH=10,DEPTH=128 myverilogfile.v

answered Mar 30, 2015 at 7:23

Morgan

20.6k8 gold badges62 silver badges87 bronze badges

Sign up to request clarification or add additional context in comments.

1 Comment

Veridian Over a year ago

What about if I am using parameterized modules? not a defines file

BobH · Accepted Answer · 2015-03-29 17:13:21Z

0

Yes, most compilers will let you do this. It is tool-specific, though, there is no standard spec for this. The most common format to do this would be +define+WIDTH=10; you would have to check the documentation or help for your compiler though (or experiment)

answered Mar 29, 2015 at 17:13

BobH

834 bronze badges

Collectives™ on Stack Overflow

How to pass parameters to a verilog module when performing synthesis?

2 Answers 2

1 Comment

Comments

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

1 Comment

Comments

Related