Verilog: Input Signal as Parameter

Question

My question may be rudamental, I am not sure if an input signal could be used as a parameter in verilog.

My question is based on a need to select one of two instances that are available based on input signal. This signal would be static post sysnthesis.

module DUT (signal1 ....)
  input signal1; // this signal to be used as parameter
  `ifdef signal1
      X U1
  `else
      Y U1
  `endif
endmodule

Here X and Y are two different modules. Alternate suggestions are also available to implement the same.

regards

---

Further Explaination:

I want only one of the two blocks of hardware after synthesis. I want a syntax that could allow the hardware configuration controlledby a signal, which is going to have a static value. Signal1 would be connected to either 0 or 1 in some other part of the design. I know this seems to be an incorrect method of doing things but it is a multi-module design and I have no control over the other block.

Answer 1

If you really want to avoid using parameters and want to use signals, depending on your synthesis tool, you may get what you want.

You need to make sure signal1 forces the output of the module that you don't want to a don't care. If your synthesis tools is smart enough (which most of them are), it will optimize that module away.

Here is an example:

module DUT (signal1, out....)
  input signal1; // this signal to be used as parameter

      X U1 (in,out_x)
      Y U2 (in,out_y)

      assign out = (signal1) ? out_x : out_y;
endmodule

If during elaboration, the synthesis tool sees that signal1 is always 1, it may optimize module Y out.

As others mentioned, this is not a common/recommended practice.

Also, you can't achieve this using `ifdef, cause they are processed at compile time. The value of signals and the fact that if a signal is statically 1 or 0 is processed at elaboration time.

Answer 2

As Morgan suggests, you can use parameters with a generate block to do what you want instead. Working example here: http://www.edaplayground.com/x/2w2

module X();
    initial begin
        $display("%m is module X!");
    end
endmodule

module Y();
    initial begin
        $display("%m is module Y!");
    end
endmodule

module top();

    parameter USE_X_NOT_Y = 1'b0;

    generate
        if(USE_X_NOT_Y == 1'b1) begin
            X U1();
        end
        else begin
            Y U1();
        end
    endgenerate

endmodule

Then when you instantiate this module you can override the parameter to get the behavior you want:

top #(.USE_X_NOT_Y(1))  top_inst ();

Answer 3

No. Instances are implied hardware blocks. You can not create and destroy hardware on the fly, unless your an evil robot.

What you can do is use an input signal as an enable/disable to both blocks so that only 1 is active, then either OR the results together or imply a mux, to select the output you want.

module DUT (
  input signal1, //sel_x
  output tx
); 
reg x_tx;
reg y_tx;

      X U1(.en(signal1),  .out(x_tx) ... );
      Y U1(.en(~signal1), .out(y_tx) ... );

      assign tx = (signal1) ? x_tx : y_tx ;

endmodule