Timeline for Verilog: Input Signal as Parameter
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 13, 2014 at 11:40 | comment | added | nguthrie | He clarified this: signal1 will be a constant, so he wants the synthesizer to recognize that it is constant and chose the module to instantiate based in this. | |
| Feb 13, 2014 at 2:58 | comment | added | user1619508 | You can't change the hardware at run time. Your question suggests that you have a fundamental misconception about how verilog, and HDLs in general, are used to design hardware. | |
| Feb 12, 2014 at 22:16 | answer | added | Ari | timeline score: 3 | |
| Feb 12, 2014 at 20:48 | answer | added | nguthrie | timeline score: 1 | |
| Feb 12, 2014 at 8:57 | history | edited | user1495523 | CC BY-SA 3.0 |
added 449 characters in body
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| Feb 12, 2014 at 8:10 | answer | added | Morgan | timeline score: 0 | |
| Feb 12, 2014 at 7:47 | history | asked | user1495523 | CC BY-SA 3.0 |