8
votes
Accepted
Why can't you mix edge signals with level signals in SystemVerilog for synthesis?
Your example, and the standard negedge rstN do not have the same behaviour. Let's see why.
I assume we are trying to make a positive edge clocked D-FF with an ...
- 73.8k
7
votes
Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?
They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value ...
- 9,139
6
votes
Accepted
Is it possible to create a PLL purely in digital design, if so how?
This is definitely possible. It is called an all digital PLL. Instead of a VCO, you use a numerically controlled oscillator, or NCO. An NCO is basically just a counter, called a phase accumulator, ...
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6
votes
Accepted
Techniques to develop software and hardware of a SoC in parallel
There are also companies that develop Software (SW) and RTL in parallel and in cooperation between SW and RTL developers. Such development is typically done in small iterations where each iteration ...
- 276
5
votes
Accepted
Including one module in another module with variable
You need to go back to basics.
Verilog is a hardware description language, not a programming language. Your code is describing hardware.
Let's see what your code is trying to infer:
...
- 73.8k
5
votes
Are Verilog and VHDL Register Transfer Languages?
RTL is a style of coding where clocked elements are expressly implied. This is generally done because synthesizers are not generally designed to design state machines on their own. While they often ...
5
votes
Accepted
When to set defaults for VHDL generics
My thoughts
It's good practice to always mention a default value to generic during entity declaration because it makes sure ...
- 11k
5
votes
Accepted
Is it a good practice to put assertion statements into VHDL RTL code to aid in simulation?
Assertions are supported in VHDL at different severity levels (\$\color{red}{\text{Error}}\$, \$\color{blue}{\text{Note}}\$ etc). You may use it to validate different properties/specifications/...
- 11k
5
votes
Multiplication in VHDL by a fraction
In the testbench, there are numerous values listed for same simulated time.
From the language reference:
The delay values supported with the after clause do not cumulate, but all relate to the same ...
- 3,340
5
votes
Why doesn't this NPN Transistor XOR Gate work
simulate this circuit – Schematic created using CircuitLab
Figure 1. OP's schematic redrawn in conventional layout with signal flow from left to right and current flow from top to bottom.
This ...
- 188k
4
votes
Quartus 10166 error: "Always_comb construct does not infer purely combinational logic"
It's a typo. In the GameOver state, you have load_dcard3 = 0 twice and don't assign to load_pcard3.
- 6,084
4
votes
Accepted
'1011' Overlapping (Mealy) Sequence Detector in Verilog
The error is caused by mixing the combinational State assignment block with the sequential output block. The combinational state assignment block and the sequential output block have different ...
- 2,369
4
votes
'1011' Overlapping (Moore) Sequence Detector in Verilog
Your state variable is too small. You have 5 states, but your variable is only 2 bits wide. It must be at least 3 bits wide. Change:
reg [1:0] PS,NS ;
to:
...
- 10.9k
4
votes
Debounce circuit design in Verilog
Debouncer
This debouncer assumes that its input is synchronised to the clock.
The output will only change state when the input has been in the opposite state for N clock cycles, i.e. a form of ...
- 930
4
votes
Are Verilog and VHDL Register Transfer Languages?
While previous answer doesn't directly answer the question, it provides a common understanding of how RTL should be read regarding digital design topics, at least according to my engineering and ...
- 412
4
votes
How to check if all the signals used have been reset in a VHDL process?
What tool do I use to ensure that all signals and variables used inside a process are assigned an initial value in the process, maybe when reset is asserted or maybe every clock cycle?
Same as every ...
- 111k
4
votes
Reading a file in Verilog
To read integer values (positive and negative) in decimal format, you can use the $fscanf system function. Refer to IEEE Std 1800-2017, section 21.3 File input/...
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4
votes
Accepted
Verilog generate block error
You cannot, and there is no need to put the cordic module instantiations inside an always block.
...
- 9,139
3
votes
Accepted
What is the difference between a hard module and a softmodule in RTL verilog code?
Soft cores are standard logic modules, written in Verilog or VHDL. They are called 'soft' because they are implemented in the re-programmable logic of the FPGA. You can edit and modify a soft module ...
- 1,510
3
votes
Accepted
SystemVerilog same function, different simulation results
Your problem is the rules for Verilog expression bit length say that operands get extended to their context determined lengths before applying the operators. In the expression:
...
- 9,139
3
votes
Accepted
Verilog code to drive a signal high always
The always block works only if there's something to "trigger" it. In your example, there were no variables on the RHS of any statements, so ...
- 185k
3
votes
Verilog code to drive a signal high always
In Verilog, you can write
reg b = 1;
And then never make another assignment to it. But that's not a good coding strategy. SystemVerilog simplified the rules and ...
- 9,139
3
votes
Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers?
At the very least, people involved in development of those HLS tools will have to know how they work and thus understand RTL in details. Just like with general programming nowadays, when you have ...
- 26.2k
3
votes
Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers?
Eventually, the compiler more or less wiped out the assembly programmer. But it took a long time, and there are still a few paid ones about, optimising high speed functions to the Nth. There are more ...
- 184k
3
votes
Accepted
High impedance in RTL Verilog
Unless you are using SystemVerilog, you cant declare a constant like that.
Instead use the replication operator. {(WIDTH){1'bz}} is a ...
- 73.8k
3
votes
Determine which clock has arrived first
Latch clock A on the rising edge of clock B. If the result is high then A arrived first.
Of course this is assuming you have zero setup and hold times on the data inputs of your latches or that you ...
- 7,072
3
votes
Relation between RTL and Verilog modules
One of the problems with many courses is that due to time pressure they try to teach concepts with problems that are too small to need those concepts.
A design is basically a hierarchy of modules. In ...
- 23.7k
3
votes
Accepted
How to design Gray code synchronous counters of large widths using SystemVerilog?
The design is partitioned into 2 parts - one for combinational logic and another for sequential logic.
In the sequential logic part, an always_ff block is used. Counter is an internal signal used to ...
- 2,369
3
votes
Accepted
3
votes
Accepted
How to check if all the signals used have been reset in a VHDL process?
There are industry-standard formal verification tools like QuestaSim Autocheck which can be used for variety of static and dynamic checks on various aspects of RTL design at the earlier stages of ...
- 11k
Only top scored, non community-wiki answers of a minimum length are eligible