13
votes
How much does it cost to have a custom ASIC made?
Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about $400 at a 350x350um size which ...
- 555
11
votes
How much does it cost to have a custom ASIC made?
In addition to answers provided here, which remain accurate, the most affordable option yet to surface is provided by Tiny Tapeout.
You can get a design on a chip for as low as $20*, which brings it ...
- 263
11
votes
Identifying an edge INSIDE an 'always' block
Assuming motorruns is intended to be a signal rather than an asynchronous reset, then for synchronous logic you shouldn't be using the signal in the sensitivity ...
- 73.7k
9
votes
Accepted
in what order does a VHDL program run in an FPGA
You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
- 43.1k
9
votes
VHDL: is there a way to create an entity into which constants can be passed?
Add a generic clause to your entity. It allows you to pass in e.g. constants:
...
- 3,987
9
votes
Accepted
SystemVerilog threads execution order
The fork/join_none construct schedules a thread to start in the current event region when the parent thread suspends or terminates. The way your loop executes, ...
- 9,139
8
votes
Why is my Karatsuba multiplier not giving right answers for large numbers?
That's a lot of code to go through, so you can break the problem down to debug it: thoroughly check the 2x2 module to make sure it works. Then check the 4x4 module, etc. This should narrow your ...
- 10.8k
7
votes
Why we need non-blocking assignments in Verilog?
Lets simplify things by assuming a and b have initial values 1'b1 and ...
- 4,498
7
votes
Accepted
Why Hardware Description Language?
Your interpretation is more or less correct at the first glance, but I think there are still some misunderstanding.
The term "script" you use isn't quite appropriate. The "script" ...
- 16.4k
6
votes
Accepted
Are Verilog if blocks executed sequentially or concurrently?
Sequentially. Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a ...
- 41.8k
6
votes
Accepted
VHDL: is there a way to create an entity into which constants can be passed?
Yes, it is called a 'generic':
I could show an example here, but there are plenty of example on the WWW once you know what to look for: https://www.nandland.com/vhdl/examples/example-generic.html
- 14.7k
6
votes
Accepted
Addition of two hex numbers in Verilog gives wrong result
You’ve declared your constants as 8 bit values with the 8’ prefix. So 0x63 + 0x63 = 0xc6 which is correct. If you want a 32 bit result then use the 32’ prefix on your constants.
- 7,105
6
votes
Vivado Simulation Running Very Slow
Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation.
One trick you can do is speed up your blink rate just for the ...
- 3,433
6
votes
Accepted
Basic addition not working as expected
Your problem is the add+ operator has higher precedence than the xor ^ operator. Put parentheses around the expression
...
- 9,139
5
votes
Accepted
Net type, variable type, data type and data objects
No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog.
When you ...
- 9,139
5
votes
Accepted
Are nested modules allowed in Verilog?
I do not think it is allowed, may be if you want to do, you should use System Verilog. More information is available in this link.
- 66
5
votes
VHDL: is there a way to create an entity into which constants can be passed?
Since VHDL 2008, you can also make output an unconstrained port and then infer the counter length from that port, as given during instantiation:
...
- 691
5
votes
Accepted
Why would this cause a latch?
The always block is evaluated every time i_S or i_V changes. You haven't specified what the value of o_R should be when i_S is false, so the simulator and ...
- 31.8k
5
votes
Accepted
Why does “non blocking” assignment in Verilog seem like a misnomer?
It isn't the assignment that's being "blocked", it's the evaluation of the statements within the process.
First of all, in both cases, all of the statements are evaluated on every clock ...
- 184k
5
votes
Vivado Simulation Running Very Slow
F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of ...
- 11k
5
votes
Accepted
Why does adding "& 1" to an assign statement produce a completely different synthesis?
The unique thing about Verilog compared to other programming languages is the concept of operand width and the context of operands and operators with different widths. The widths of certain operands ...
- 9,139
5
votes
Accepted
FPGA applications in power electronics
I don't have any book or academic references unfortunately, but I can offer a little experience, and explanation.
I led an FPGA based development of a resonant power system, back in 2010-2012 or so.
...
- 53.1k
5
votes
How do I create a 2D array in Verilog?
The syntax in your code is only supported by SystemVerilog (IEEE Std 1800). It is not supported by Verilog (IEEE Std 1364).
In Verilog 1364-2005, section 4.9.3 Memories (emphasis added):
An n-bit ...
- 10.8k
5
votes
Accepted
Why does this Verilog code work without "wire" statements?
Is this an error?
This is not an error. Declaring these signals is optional. Refer to IEEE Std 1800-2017, section 6.10 Implicit declarations:
If an identifier is used in the terminal list of a ...
- 10.8k
5
votes
SystemVerilog threads execution order
Threads are by their essence asynchronous — you may not predict when an individual thread begins, ends, or executes a particular command.
In other words, the order of your output lines is ...
- 1,325
4
votes
Maximum frequency for a FPGA-based square wave signal
If you don't feed the clock out with a DDR flip flop, then the max frequency you would expect to see is \$f_{clk}/2\$. The reason for this is that the output can only change once for every complete ...
- 41.8k
4
votes
Accepted
Maximum frequency for a FPGA-based square wave signal
You can't generate a frequency higher than the internal clock. If you have access to a Phase Locked Loop or PLL, you might be able to.
Usually the external clock gets fed into an PLL and the internal ...
- 93.2k
4
votes
Accepted
Eliminate VHDL inferred latch in case statement
The reason for the latches is due to the fact that the outputs of your case statement are not assigned for every possible case selection. So you have created a storage element without a clock - which ...
- 4,129
4
votes
What exactly lies between an HDL and a circuit?
are HDLs really used to design digital devices from scratch?
Having done exactly that for many years, I can assure you that, yes,
real chips are developed with HDL.
For that we use, just like with ...
- 14.7k
4
votes
HDL code convention for register resets
It won't make any difference in the synthesized hardware. But writing in an HDL, or more precisely, writing at the register transfer level (RTL) abstraction should take you away from the structural ...
- 9,139
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