Questions tagged [rtl]
Register Transfer Level (RTL) is a logic design abstraction where digital circuits are described in terms of storage elements (registers) and the combinatorial logic operations that occur between them. RTL is one technique of describing a digital system using hardware description languages such as VHDL and Verilog.
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Why doesn't this NPN Transistor XOR Gate work
I'm trying to build transistor logic gates in tinkercad and am stuck on the XOR gate. I built the circuit below but it doesn't work. The led light won't turn on at all regardless of what position the ...
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Issue VHDL custom AXI4-STREAM IP generating TLAST
I'm currently debugging a custom AXI4-Stream RTL module that I'm using to transfer data from the XADC to the DMA on a Zynq SoC. The goal of this module is to collect a fixed number of samples (...
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Architecture of variable size data combiner in RTL
Data comes in from a module where the valid bits are going to be between 1 and 32. A word comes along with data that indicates how many bits are valid starting from the least significant bit. This ...
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Creating entity/module containing IP from different vendors
In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
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How to Resolve LINT-1 Warning During Synthesis?
I am currently working on the synthesis stage of a hardware design project and encountering a specific warning from the LINT-1. I'm seeking assistance to resolve this issue.
Tool: design compiler
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Synthesis with Verilog Parameter AUDIO_DW = 32 Results in LINT-1 Warning
I'm working on a Verilog project and encountering a warning during synthesis. When I set the parameter AUDIO_DW = 32, I get a ...
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
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How do I implement a simple axistream by my self bus in VHDL?
I'm working on a design right now but I'm struggling with the axistream bus. I just want to be sure that I'm understanding well how it works. To do so I'm using the uvvm library to do a generator that ...
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Generate random numbers in a range with some others excluded
I need to generate random number between 0 and 191. This will fit in 8 bits. Then depending on certain constants being defined or not, certain slices of this range shall be included or excluded. e.g ...
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How to find syntax error in RTL file quickly?
My company uses custom flow that is accessed via makefiles to compile the RTL and testbench code and run the simulation. The simulator cannot be accessed directly to open in GUI. The makefiles submit ...
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Why does the resistor need to be placed before the junction in an RTL NOT Circuit
I am trying to implement a simple inverter using transistors. I am confused why placing the resistor between the junction and the LED will not work, but placing the resistor before the junction does ...
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Why the prohibition against blocking statements in FF synthesis?
In most intros to Verilog, it's basically stated as a law that "blocking is for combinational and nonblocking is for sequential". That turns out to be a good rule of thumb because of how ...
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Why can't you mix edge signals with level signals in SystemVerilog for synthesis?
In a number of sources I've come across, it's mentioned that for sensitivity lists which include an "edge", you cannot include other signals in the sensitivity list if you want synthesis to ...
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In SystemVerilog, is the set of operators usable in a continuous assignment smaller than that usable in an always statement?
My question is, essentially, as stated in the title. For what it's worth, it's prompted by a comment made by Stuart Sutherland on page 256 of his RTL Modelling with SystemVerilog:
The primary RTL ...
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