Frequency range for ESR of decoupling capacitor used in Xilinx FPGA

Question

I am trying to do own PCB design based on Xilinx FPGA Zynq 7010. Their application note (UG933) provides recommended decoupling capacitor values with its ESR range, but they do not specific the frequency range. In this case, how do I pick capacitor with proper ESR?

I know those are suggested values, but which frequency range? Other chips from Xilinx mention specific frequency range for its ESR, but this particular one doesn't. This is my first time designing FPGA PCB design, and I would like to approach carefully.

Answer 1

By ESR the Zynq documentations mean only the effective resistance in a simple first order RLC model of the capacitor, where the ESR is not dependent on frequency.

As an example, many PDN appnotes say that to keep ripple low enough due to capacitance, you need at least certain capacitance, and if that capacitor has certain ESR, you need larger capacitance for the combination of keeping ripple low enough due to ESR and capacitance.

The ESR part being variable beyond the first order RLC is not considered in many applications, because compared to the total impedance, the ESR change is rather insignificant compared to the change in |Z| when frequency is varied around the resonance point.

So basically, if they already state a capacitance value and capacitor size, and given suggestions where exactly to place the capacitors and how to draw the PCB power planes, they have already simplified the effects of capacitance, inductance and required frequency range down to a simple rule to just get a capacitor with small enough ESR.

Edit : In the Xilinx/AMD UG933 you link to, they explain the first order RLC model in Figure 4-3 on page 23. So the ESR has no frequency range, because in that model it is only the ESR at resonance frequency where the part impedance equals the resistive ESR, as reactance from ESL cancels the reactance of the capacitance.

Many capacitor manufacturers such as TDK also give this simple RLC model and state the ESR for their capacitors, even if they do provide the full ESR curve vs frequency.

Simsurfing gives the full ESR curve, so for compatibility with UG933, look at the resonance point where |Z| value curve is at minimum and it equals the ESR value curve.

Answer 2

When an ESR is asked for, either the frequency range is given by context, or the minimum will suffice.

For PDN purposes, frequencies of interest are generally some kHz to 100MHz or so. Higher frequencies are increasingly difficult to treat at the PCB level, depending on required impedance: the inductance of pins or balls, bond wires, etc. limits performance of low impedance interconnects such as for SoCs, hence why they must have onboard bypass. For the number of pads/balls these devices have, and the impedances they require, the practical design cutoff is typically 50-100MHz. Smaller devices, with less severe impedance limits, can depend more on board design.

There's nothing prohibiting the construction of RF transmitters for instance, but indeed, typical amplifier design uses decoupling inductors specifically to raise the impedance between signal and supply nodes; an impedance above Zo affords series decoupling, just as an impedance below Zo affords shunt decoupling. This, along with techniques like 1/4 wave structures to notch out carrier and harmonics, affords high isolation in various bands or ranges, without demanding impedances and ratios.

Or for another example, there are various integrated RF microcontrollers, from ST, ESP, TI, etc., operating in the mid 100s MHz to low GHz, which require fairly modest bypass near the RF section (one or two caps, say), because the power levels are low and thus impedances fairly modest.

Regarding context, there's both the context of the application itself (operating frequencies and harmonics), and the capacitor's context, i.e. what it's connected to. Typically, ESR is most important at the characteristic frequency with respect to connected inductances (e.g. component body and trace inductance). And typically these will be in the low MHz range, comparable to (below or near) the SRF of the part itself (which is defined by its body inductance).

Answer 3

If you know the resonant frequency of an RLC circuit, you can answer this yourself using C and ESL.

The impedance of the Cap will be a minimum with the value of ESR when equivalent series inductance ESL or its impedance X{L} cancels with the negative X{C} at the series resonant frequency.

https://docs.amd.com/v/u/en-US/ug933-Zynq-7000-PCB

Inductance is simply the geometry of the conductor not including the pads and trace you add to this. Consider the cap size and figure it out in nH/mm with including layers in series and/or in parallel.

This means they want you to use the smallest Cap with the lowest product \$ESL*C= \omega ^2\$ and lowest ESR*C = Tau product .

They show that adding a few mm traces is too much. This is because conductors with a certain Length/width ratio are about 0.8 nH/mm +/50% for a wide log range of aspect ratios for l/w.

We used these nomographs back in the 70's to save time in the days when slides ruled. (pun)

If caps ESL are not specified, consider that the trend with size is fairly linear for 2:1 = L:W. ratios. Lower ESL caps are 1:2 ratio are available in some types for ceramic.

You can plot all 3 caps on this chart to get the picture.
Learn to include trace ESL in your simulations when it matters.