Questions tagged [decoupling]
The decoupling tag has no summary.
155 questions
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Is there any relation between capacitance seen by I/O driver and required power decoupling?
Say an FPGA is constantly (i.e., at frequency F) toggling K output lines that each have capacitance C. Is there anything we can say about the minimum decoupling capacitance that must be present on the ...
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Are Controlled ESR Capacitors Extinct?
I was researching the use of controlled ESR capacitors for decoupling and I wondered what part numbers there are for these capacitors.
For those who don't know controlled ESR capacitors are MLCC ...
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Problems with I2C-Extender
I've built a stepper motor control for my magnetic loop antenna. Besides the motor, I also have a 3-axis compass module on the loop to be able to read the heading from a distance.
The sensor runs via ...
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2
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NE555 frequency affected by nearby FS1000A
So here is my schematic:
TLDR;
Basically it is a boundary wire detector transmitter, pushing a 50 kHz 150 mA current into a wire, Q1 and Q2 are used to detect wire interruption, if wire is ...
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How can interplane capacitance still be preserved if decouplings capacitors are placed directly at the via of the BGA?
Assuming you routing a PCB were you using an IC with a BGA package.
Your mission is to:
Preserve the inteplane capacitance
Fit decouplings capacitors (0201 or 0402) onto the BGA vias
Not using blind ...
- 1,466
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3
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Frequency range for ESR of decoupling capacitor used in Xilinx FPGA
I am trying to do own PCB design based on Xilinx FPGA Zynq 7010. Their application note (UG933) provides recommended decoupling capacitor values with its ESR range, but they do not specific the ...
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Uses of Feedthrough Capacitors on PMIC
I am currently designing a PCB which will use the Texas Instruments LP876242-Q1. The board is a similar board to their TIDA-020047 reference design, so I am studying their design decisions. One ...
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Connecting Power pins on BGA packages
For BGA packages, I never see people tying power/GND pins together on BGA package (e.g. tying +1.1V_FPGA pins together as shown). Usually I see one ball to one via like how the GND is layout as shown. ...
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Decoupling output of direct grid voltage class E amplifier
For a university project I'll implement some middle power (100 W) high frequency inverters (~500 kHz) with pulsed DC ~300 V DC output. The output current must be decoupled from the supplier grid due ...
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Coupling/decoupling power supplies: how? [closed]
I'm adding a hi-Z adapter to a solid-state amplifier that is powered from the mains through a transformer and regulator. The hi-Z adapter is powered by 24 volts DC, so i need an external power supply ...
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What are the functions of these capacitors connected to the output of a efuse?
I am a beginner in electronics, and I am studying a LiPo charger circuit:
https://www.elektor.com/products/diy-lipo-supercharger-kit-v2-by-greatscott
This is the full schematic:
https://s3.eu-central-...
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2
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Why don't we use decoupling capacitors for open-drain outputs?
If an IC with open-drain outputs (and hence pull-up resistors) is used, we of course put decoupling capacitors on the IC supply, but why don't we also add decoupling capacitors between the power pin ...
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Decoupling capacitors where VDD/VSS pins are spaced apart
On previous PCBs I've laid out, I've always been able to place decoupling capacitors easily due to VDD/VSS pairs being close together. However, I'm now working on a design that's using a chip (ISSI ...
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Decoupling Caps Topology from Microchip MPU Datasheet
I am trying to develop a power distribution network for this device.
https://ww1.microchip.com/downloads/en/DeviceDoc/MPU-SAMA5D27C-CNVAO-datasheet-60001532a.pdf
I am looking at decoupling capacitor ...
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Can parasitic capacitances be decoupled?
I was working with some IC that has a bus that is really sensitive to trace capacitance and cannot be loaded with more than 8.5 pF.
I have to bifurcate the trace to an ADC because I need to see what ...
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