Questions tagged [asynchronous]
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25 questions
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Why does the 2‑wire asynchronous handshake use this exact edge sequence?
1. Control Models
Master / Slave
The master controls the communication line (decides when to transmit or receive).
The slave transmits or receives under the master’s command.
Peer‑to‑Peer (symmetric)
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Why does my synchronous mod-19 counter goes to (2,2) -> (2,3) -> (0,2) while the asynchronous version resets cleanly?
I'm designing a mod-19 counter in Logisim using two 3-bit (mod-8) counters:
Counter A – low-order bits (0…7)
Counter B – high-order bits (0…2)
1 Asynchronous version (works)
Clock drives A directly.
...
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Vivado Simulation Bug for 4 bit asynchronous ripple counter
I am currently learning Verilog and tried to build an asynchronous counter using T flip flops.
But, during the simulation, my most significant three bits become one without any clock signal from the ...
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why does Quartus Prime shows a path as failing in case of CDC even though synchronizers are used?
suppose a signal is coming from a slower to a faster clock domain, and 2 levels of synchronizing FFs have been used, then the tool shows failing path from the launch node to the first synchronizing ...
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2DFF synchronizer output was determined to be a clock by timing analyzer
I'm the newbie in FPGA.
I want to design a frequency counter, so the design will involved some CDC problem.
Therefore, I used FIFO (I use the Quartus FIFO IP) and 2DFF synchronizer in my design.
Below ...
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What is the best way to use asynchronous ("non-blocking") delay in embedded systems?
Background
I understand, maybe I'm wrong, an asynchronous delay would be one that does not completely take over the CPU.
On the other hand, the synchronous delay remains in a loop, counting clock ...
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3 bit Asynchronous Counter
> Blockquote
In our lab, using digital trainer kit, we designed the 3 bit asynchronous counter using JK flip flops by connecting clock to pin 1, following this circuit:
We had three inputs that ...
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Self clock synchronization in NRZ-I encoding
I was going through NRZ-I encoding technique, somebody mentioned that long stream of 0's will cause loss of synchronization in NRZ-I encoding scheme. But how?
What I understand is the receiver should ...
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How to interpret timing of cascading async SRAMs
I am reading the datasheet for a 32k × 8 asynchronous SRAM (part IS61LV256AL) and wondering how to apply the timing diagram to the following circuit:
We have three identical SRAM parts with inputs ...
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
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The logic gate design of a positive edge triggered, master slave d flip flop with asynchronous inputs preset and clear?
I'm a computer science student who's trying to get a better understanding of the d flip-flop. My project assignment is to make a CMOS design of a positive edged d flip-flop using ff master slave and ...
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Can a buck converter functioning in CCM have non-linear behaviour at light load currents?
I've been designing a Simulink/Simscape model of a TI buck converter launchpad (https://www.ti.com/tool/BOOSTXL-BUCKCONV) and I'm trying to have my model fit the behavior of the device.
The board can ...
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D Flip Flop Design on Logisim
I am trying to build a D flip-flop but I can´t get rid of those red wires. Is there a way to solve this?
EDIT: I was able to fix it manually through step-by-step simulation, but I still would like to ...
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Interfacing TLC59731 with Attiny85
Has anyone had any experience communicating with a TLC59731 from an Attiny85? I'm not sure how to configure the USI to support the EasySet "protocol" described in the datasheet. I imagine I ...
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Verification of asynchronous FIFO
I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings.
The goal is to verify this design by using the Tb components, so no UVM at all. I ...
