Questions tagged [verification]
Assurance of satisfiability of all the expected requirements in either software or hardware systems.
83 questions
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Testing the total string voltage over-voltage protection in a Lithium-Ion BMS
I am testing a lithium-ion battery system with two levels of overvoltage protection. The system is equipped with:
Level 1 Protection (Cell Overvoltage): The BMS triggers switches to disconnect the ...
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Sanity Check: PSU Input, RPP, Noise Filter, Relay, Logic Level designs
I'd love a sanity check by experienced designers here, to see if I've made any obvious mistakes in my design?
Here's the PSU input stage:
Reverse polarity protection via crowbar circuit to blow a ...
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ModelSim: Non-Synthesizable Verilog Reference
Where would I find a good reference (or even cheat sheet) on the non-synthesizable functions/syntax/commands that can be used in Verilog with ModelSim?
In other words, where would I find a complete ...
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Boundary scan using SWD interface
Can boundary scan be performed over SWD interface on the ARM devices? I keep seeing that SWD is a functional 2-wire replacement for JTAG interface, but can't seem to find a definite answer if a ...
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Resistor Values for Optoisolator / NPN Circuit
I need to design a "Soft Power" circuit to turn on a power supply when the PFW line is high (5V). I came up with the following drawing, after using the following "sources" for ...
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A curious case of combinational logic
I am running circles around the following scenario and have no idea of where the solution will be. The task is to implement the following gray to binary converter in SystemVerilog:
I adapted a ...
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Possible GND Conflicts in My PCB
I have the following schematic as the verification and validation setup for our DC-DC converter:
The idea is that by using a DAC, we can manipulate the output voltage. We plan to send commands to the ...
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How can a designer be sure to authorize only legit ICs? How is performed? How are cloned ICs prevented to be activated?
The above diagram is from the IC Activation (locking/unlocking) slide of Fighting against theft, cloning and counterfeiting of integrated circuits by Lilian Bossuet Associate Professor, CNRS Chaire of ...
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The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
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How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
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ESD Workstations in Manufacturing Facility
I am a manufacturing engineer for a company that just inherited a large electrical build. I am struggling to find ESD information for multiple workbenches. This is my last resort so I am hoping you ...
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Ascertaining that a BGA's decoupling capacitance is good enough
BGA parts often have a large number of power pins in the middle of the package. It is of course important to ensure that the power rail has been sufficiently capacitively decoupled. How can one go ...
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Transformer Design for a Series Resonant Converter
I am determining the Area-Product of the core required for a transformer to be used within a series resonant converter. The specifications are as follows:
Switching frequency = 400 kHz
Primary ...
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Current values verification check without ammeter [closed]
Given the following circuit with my current directions (the ones I highlighted with red):
So \$ I = - 2 A, I' = -1.5 A, I_x = \frac{1}{2} A , I_y = -1.5A , V_x = -1.5 A \$
Is this valid?
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How to use "question mark" in start method of UVM?
I am trying to modify the existing code using the start() method in UVM.
Basic code is below:
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