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I am reading JEDEC DDR3 specification, and so many other documents on DDR3 guidelines. Before I move to pcb prototyping, I just need a confirmation.

I connected all my lines, respected the grouping, length matching, impedance matching, via size. My DDR3 type is 1333.

Question:

If I keep the CPU and Memory IC close (less than 2 cm), do I need to take care of trace length (I mean their absolute length, not their matching)?

My opinion is that it doesn't matter because the current travels at half the speed of light on a FR4 pcb board. Even 1cm more should not matter much. And my SDRAM controller will take care of the rest of the details for me.

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  • \$\begingroup\$ 1 cm is significant skew at 1333 MHz what is your budget for skew and how many ps margin do you want to lose? and what dielectric is used, layout etc... Not all FR4 is the same Er and tan delta. Base Cu , plating th. and substrate thickness with 1333MHz will reduce Er effectively to 2.5 on Getek from 3.8 > You have a bit to learn. You need an immersion Au due to skin depth \$\endgroup\$ Commented Mar 22, 2018 at 16:52
  • \$\begingroup\$ Do you have ANY design specs for skew and jitter? If not why not? Have you heard of the shmoo test to find the optimal settings? +/- tolerances on V, clock and skew en.wikipedia.org/wiki/Shmoo_plot \$\endgroup\$ Commented Mar 22, 2018 at 17:04
  • \$\begingroup\$ Thanks for your comment Tony. I will ask the manufacturer for the best combination according to my goal. They may be helpful. My cpu is a Allwinner H5 and the ddr3 is Winbond's W631GG6KB. And I don't have any ATE at hand > No shmoo (thanks for mentioning this, I learnt something). I am an hobbyist, willing to learn ;) \$\endgroup\$ Commented Mar 22, 2018 at 18:08
  • \$\begingroup\$ Also look at similar traces on MOBO and DDR cards \$\endgroup\$ Commented Mar 22, 2018 at 18:54
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    \$\begingroup\$ ti.com/lit/an/sprabi1c/sprabi1c.pdf \$\endgroup\$ Commented Mar 22, 2018 at 19:07

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It depends on how much margin you have. At 1333, your bits are ideally 750ps wide. In reality due to noise, reflections, edge rates, etc. you will have some smaller interval of valid data. As long as the delay difference between your traces is not a significant portion of your data valid time, you should not have a problem. Since your traces are so short, the PCB would have to be pretty poorly routed to get a significant delay difference .

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  • \$\begingroup\$ Thanks crj11. Is there any data in the ddr datasheet that could help with the ideal length, or should I rely on 1) testing (trial and error) 2) spending my house to buy a signal integrity soft to be sure 3) be reviewed by a pro on that part? \$\endgroup\$ Commented Mar 22, 2018 at 18:02
  • \$\begingroup\$ A rule of thumb is that as long as your edge rates are not a significant portion of the propagation delay on your net then you don't need to worry about transmission line effects. Assuming ~100ps edge rates, with 2cm you will need to properly terminate the signals. If the signals are correctly terminated and have good impedance control it should work. Keep in mind that vias affect the impedance, so if you can't route everything with minimal/no vias, then you are more likely to have problems. The clocks are the most important to get correct. \$\endgroup\$ Commented Mar 22, 2018 at 18:09
  • \$\begingroup\$ I only have two vias for each transmission line: one from below my cpu and the other from below the ddr ic. I really thought the design to be as simple and focused on a very precise need as possible. Thank you so much for your invaluable help. \$\endgroup\$ Commented Mar 22, 2018 at 18:28
  • \$\begingroup\$ how does one ensure that the via has 50 ohm impedance, is that possible or required? \$\endgroup\$ Commented Apr 25, 2023 at 9:09

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