You mention the following layer stackup:
| Layer |
Function |
| L1 |
SIG+GND |
| L2 |
GND |
| L3 |
High speed |
| L4 |
GND |
| L5 |
Power 1 |
| L6 |
Power 2 |
| L7 |
GND |
| L8 |
High speed |
| L9 |
GND |
| L10 |
SIG+GND |
With all copper layers being equidistant like you showed in the example 6L stackup (which is rather unusual, but I'll roll with it), your reference planes will be as follows:
| Layer |
Function |
Ref |
| L1 |
SIG+GND |
L2 |
| L2 |
GND |
- |
| L3 |
High speed |
L2/L4 |
| L4 |
GND |
- |
| L5 |
Power 1 |
L4/L6 |
| L6 |
Power 2 |
L5/L7 |
| L7 |
GND |
- |
| L8 |
High speed |
L7/L9 |
| L9 |
GND |
- |
| L10 |
SIG+GND |
L9 |
For each forward current in a layer there will be an equal amount of total return current in that layer's reference planes. When there are two reference planes the magnitude of the return current in each will be distributed based on the impedance of the return path. This poses some problems given your stackup.
First, your power layers are the same distance from each other as they are to the ground planes. This means that you will see return currents from one supply rail being induced in other supply rails on the opposing power layer. These return currents will be superimposed on your forward currents, producing ohmic and L∙dI/dt voltage noise due to parasitics. The magnitude of this noise will depend on how much current you're moving around, your layout, and your decoupling practices.
Additionally, your high-speed layers also share a reference plane with your power layers. Large current transients will cause localised ground bounce in L4 and L7, which will introduce noise into your high-speed signals. This is largely mitigated by the use of differential signals on the high-speed layers, since the ground bounce is likely to induce common-mode noise rather than differential-mode noise, which is easier for the receivers to reject. However, you do need to be careful to avoid routing your differential pairs too close to current density hotspots, since the separation between the pair of traces can result in differential noise.
Another issue with putting your power layers in the middle is that you end up with a larger loop area between your components on the outside and your power delivery planes. This is manageable with really good decoupling practices and using ground reference vias adjacent to your power vias, but you do need to be careful about it and avoid routing your high speed stuff too close to power vias. You also have to worry about return currents flowing in L2 instead of L4 when feeding power up to components on the top layer.
Based on the stackup and material specs that you provided, a 100Ω differential stripline would need to be 4mil trace with 10mil spacing. If you used a coplanar stripline differential pair you could go to 5.4mil trace with 12mil pair spacing and a 20mil gap to the coplanar ground. This would take up more space in your layout, but would avoid needing to go all the way down to 4mil traces. Whether or not this matters depends on your board house's capabilities and cost adders.
All of this is workable, but typically we don't use stackups with every layer the same thickness, and you can probably do better. What you typically want to do is have your layers organised into closely-spaced pairs with one ground layer and one signal or power layer.
I'd start with a wide core in the center to keep the two power layers away from each other. Then I'd have a very thin prepreg between L4-L5 and L6-L7, to increase the distributed interplanar capacitance in the power delivery network. Then I'd have the L2-L3 spacing be smaller than the L3-L4 spacing (and the same on the mirrored side) to turn your high speed signals into an asymmetric stripline where L2 is the preferred reference plane, thus better separating the high speed return currents from the power return currents. I'd then ensure that every via carrying a high-speed signal or power has a closely-spaced ground reference via next to it. However, you may need to pay for HDI (microvias) or backdrilling to eliminate the stubs when using vias to get from your outer-layer components to the high-speed layers.
An alternative approach would be to move your high-speed to the outer layers and route them as microstrips instead of striplines. This eliminates the need for microvias or backdrilling because you're either staying on the same layer or going all the way through to the opposite outer layer. This may make BGA/LGA fanout more difficult though.
If you want some good reading material on this front, take a look at Eric Bogatin's book "Signal & Power Integrity Simplified".
