531 questions
-2
votes
1
answer
95
views
How do machine read the instructions of Risc-v [closed]
How do machine read the instructions?
for example:
if it is a R-type, machine first read the opcode to know the type of instruction,and base on the type, read the instruction from right to left,to ...
- 11
1
vote
1
answer
301
views
Attack Lab Phase 4: rdi gets the wrong value despite correct assembly being put on stack
I am working on phase 4 of the buffer overflow attack lab, where the solution is is to use ROP (Return Oriented Programming). The idea is that you are given a "farm" where you will look for ...
- 43
-1
votes
1
answer
54
views
x86 instructions, interpretation by stack pointer
The following instructions:
0xffffd096 push eax
0xffffd097 push 0x41414141
Oxffffd09c push 0x42424242
affect the stack as follows:
0xffffd024|+0x0000 "BBBBAAAA" <- esp
...
- 49
0
votes
1
answer
70
views
x86 opcodes for the xor instruction, cannot find detail required in manuals
Some instructions with corresponding opcodes:
xor eax, eax \x31\xc0
xor ecx, ecx \x31\xc9
xor edx, edx \x31\xd2
xor ebx, ebx \x31\xdb
Could someone please explain the calculation ...
- 49
1
vote
0
answers
185
views
what bits in an arm64 instruction is the operation code?
10101001101111100111101111111101
a9be7bfd
this is the binary for
stp x29, x30, [sp, #-32]
I know bit 31-30 is the 64 bit-32 bit bits, bits 0-14 is for the registers, and bits 15, 21 is for the ...
0
votes
1
answer
130
views
How OS code gets executed by microprocessor when microprocessor have limited set if instructions / opcodes
I've been trying to understand and did lot of online research but still have doubt:
If processor understands only opcodes (which are limited) then why is it possible to execute operating system code? ...
- 9,065
0
votes
0
answers
113
views
LLVM invalid cast opcode for cast from 'i64' to 'i64'
I'm trying to use LLVM Create and replaceAllUsesWith to modify the (A+B+C) calculation to (A*B)-C
The ReplaceInst.cpp code I wrote is this,
// Traverse Instructions in TheModule
void TraverseModule(...
- 13
0
votes
1
answer
37
views
Can't supply assets via call Solidity
I have contract and want to supply testnet USDC to Compound on Sepolia, but this doesn't work with call opcode in Solidity
// SPDX-License-Identifier: MIT
pragma solidity ^0.8.19;
import {IERC20} ...
- 11
-1
votes
1
answer
96
views
How to print out the literal value of a Spir-V OpConstant?
I am have a Spir-V parser from Github, which is capable of processing and modifying the Spir-V binary. At the moment, I just would like to print out the literal value of the OpConstant variables.
...
- 376
0
votes
0
answers
80
views
How can an address that receives bytes through movs transfer bytes to another address that receives bytes through movups
Memory Viewer
I need to assign the value of the upper address to the lower one, but they have different commands, the first one has movups, and the second one has movss
I have this code in an auto-AOB ...
- 5
0
votes
1
answer
1k
views
Extracting opcodes from arm64 (ARMv8.5-A) instructions
I need do come up with some wildcards to match certain instructions.
For instance, on x86, to match most CALL instructions the following pattern will suffice:
E8 ?? ?? ?? ??
where E8 is the opcode ...
- 309
0
votes
1
answer
95
views
Invalid opcode in Metamask and Ganache
When running a contract I am getting in remix an invalid opcode as well on Metamask, the contract that I am running is quite simple:
// SPDX-License-Identifier: MIT
pragma solidity ^0.8.0;
contract ...
1
vote
1
answer
197
views
Mysterious ARM Opcode
In decompiling a hex file for a Texas Instruments ARM (Thumb 2) Cortex-M4f processor (CC2652RB), I have come across an opcode that I can't figure out.
What does "90 FF FF 00" do (maybe the ...
- 297
0
votes
2
answers
1k
views
Disassembling bytecode into opcodes across different EVM versions
I need to disassemble bytecode into opcodes across different EVM versions, to make it agnostic to the EVM version used during compilation?
As the second best option - is there a disassembler, that ...
- 895
0
votes
0
answers
28
views
Any useful way (amd64) to effect a transfer like this? pc <-- (sp) [Note the absense of auto-decrement]
That's it. Seems to be specifically absent.
Just read ('red') the instruction set, I don't see an obvious way to do this?
Looking for a way to get the same result, shorter is better of course.
(Have ...
- 173