132 questions
3
votes
0
answers
107
views
Element size in Disp8*N compression for AVX-512FP16 half-precision floats?
According to Intel 64 and IA-32 Architectures Software Developer's Manual from March 2026, the Intel half-precision FP instruction VCMPSH k1{k2}, xmm2, xmm3/m16 {sae}, imm8 is defined as EVEX.LLIG.F3....
- 6,097
4
votes
1
answer
142
views
Does Move to/from Control/Debug Registers ignore the "mod" field?
Description of this operation says that the 2 bits in the mod field of ModR/M are ignored.
In my disassembler I want to simplify it and just OR the third byte of opcode 0F 20 /r with value 0xC0, which ...
- 6,097
3
votes
1
answer
107
views
Do the bytes "00 10 A1 B3" make sense in Arm 32-bit architecture?
The bytes 00 10 A0 B3 decodes to movlt r1, #0 in the arm 32-bit architecture.
When I type the bytes 00 10 A1 B3 into the shell-storm online disassembler, it shows "N/A".
However, in the ...
- 743
3
votes
1
answer
100
views
Can I somehow tell GAS to change direction of operands?
I have the binary image of a bootloader which was written with some ancient assembler.
I want to port the assembly code to GNU assembler (GAS). We speak about the X86/16-bit
(real mode) world.
This ...
user10316237
3
votes
1
answer
109
views
Why are J1 and J2 used with XOR in ARMv6-M BL instruction immediate calculation?
I’m trying to understand how the BL instruction is decoded in the ARMv6-M architecture.
The part I don’t get is in the imm32 calculation: the values of I1 and I2 are derived using J1 and J2, but they’...
- 761
3
votes
2
answers
320
views
ARM64 add instruction preferred opcode?
ARM64 supports add (extended register) that must be used for SP register, and add (shifted register) that must be used for ZR register.
The instruction add X0, X1, X2 matches the syntax for both of ...
- 524
1
vote
1
answer
137
views
What is the proper octal representation of the encoding of the operand register in intel 8086?
The classical explanation of Intel opcodes using octal says this:
As an example to see how this works, the mov instructions
in octal are:
210 xrm mov Eb, Rb
211 xrm mov Ew, Rw
...
- 279
1
vote
1
answer
218
views
8086 memory to accumulator encoding: why do mov al, [absolute] and mov ah, [absolute] have different sizes?
mov al, [10] ; a0 0a 00
mov ah, [10] ; 8a 26 0a 00
After assembling the above 8086 assembly code using NASM, I noticed a length disparity in the resulting machine code (shown in the comments above ...
2
votes
1
answer
197
views
Why encode RISCV PseudoInstruction LI to four instructions instead of two?
Dear RISCV enthusiasts,
My question is about encoding
li t1, 0xFF00F007
When using https://riscvasm.lucasteske.dev/# the code above encodes to
0: 000ff337 lui t1,0xff
4: 00f3031b ...
- 23
0
votes
0
answers
195
views
Understanding the Funct6 field in shift immediate instruction in RISC-V
The following figure shows the instruction format of the RISC-V architecture.
Also in the following figure, that is from Computer Organization and Design, RISC-V edition, 2nd edition, the three ...
- 287
0
votes
0
answers
153
views
How are x64 instructions decoded and what is the format of the generated uOps?
I'm looking at computer microarchitecture and understanding how CPUs work in hope to perhaps design my own CPU out of logic gates. I understand that the complex nature of x86-64 instructions having ...
1
vote
1
answer
127
views
Writing an assembler: clean and efficient way to handle x64 REX and VEX encoding?
I'm working on an x64 assembler (just 64 bits, at least for now), and I've gotten decently far (I have support for pretty much all instructions, including most extensions), but I have some pretty ...
- 89
1
vote
0
answers
185
views
what bits in an arm64 instruction is the operation code?
10101001101111100111101111111101
a9be7bfd
this is the binary for
stp x29, x30, [sp, #-32]
I know bit 31-30 is the 64 bit-32 bit bits, bits 0-14 is for the registers, and bits 15, 21 is for the ...
-1
votes
1
answer
97
views
Why does operand 1 in a modr/m byte change depending on the decoding mode
I'm trying to figure out why the instruction changes from add [eax], al to add [rax], al when changing the decoding mode from x86 to x64.
The instruction bytes are 00 00
I think it might be because ...
- 33
5
votes
0
answers
130
views
Why does Intel x86 manual use +rd instead of +ro or +rq for 64-bit registers?
The description of the PUSH instruction in the Intel manual (PDF, Volume 2, Chapter 4.3, PUSH) contains the line 50+rd PUSH r64. It seems +rd is used throughout most of the instruction descriptions ...
- 128