Options Grow For Standardizing Data Movement And Sharing Resources


Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh Choudhary, senior principal engineer at Intel; Siamak Tavallaei, senior principal engineer at Samsung SSI; and Mohsen Asad, senior director of technology at Credo. What follows are excerpts of a disc... » read more

Blog Review: May 20


Cadence's Siddh Virani demonstrates how to import and integrate foreign language logic into PSS on both Target and Solve platforms, opening possibilities for code reuse and cross-language collaboration. Synopsys' Sumit Vishwakarma finds that AI model training and inference workloads are forcing the industry to rethink not only how much compute fits in a rack, but how servers are architected ... » read more

Chip Industry Technical Paper Roundup: May 19


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Micro-Transfer Printing on Silicon Photonics: Tutorial, Recent Progress and Outlook 🔗 Ghent U., imec Challenges and prospects of 2D electronics for future monolithic CFETs 🔗 SKKU, Hanyang U. et al. A Device-Physics-Informed Artific... » read more

Confusion Grows With More Interconnect Options And Tradeoffs


Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Chip Industry Week in Review


Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

Chiplets Need A New Workflow


Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out. ... » read more

Flash Getting Stacked High-Bandwidth Version


Key takeaways: A new HBF 3D flash stack is similar to HBM for use in AI processing. HBF capacity will be much higher, allowing static storage of AI model weights, with optimized read speed. Samples are due out later this year, with accelerators featuring it coming out next year. AI inference using modern models requires billions of parameters, and moving them to where they c... » read more

Gates Add Functionality, But Wires Create Problems


Key takeaways: While transistors see continuous improvement, wires keep getting worse because of the smaller geometries and larger chip sizes. There are limited ways to avoid such problems, but the biggest impact will come from floorplanning. Analysis today is not adequate. New developments, such as backside power and 3D integration, provide temporary relief but new materials are a d... » read more

Scaling PCIe Controllers for AI Bandwidth: A Multistream Architecture Analysis for 64 GT/s and 128 GT/s


Scaling raw lane speed without rethinking controller microarchitecture leads to diminishing returns. It introduces multistream architecture, a controller‑level re‑architecture designed to sustain effective bandwidth under mixed and small‑packet workloads. This paper examines the architectural inflection point at PCIe 6.0, details transmit‑ and receive‑side changes required for multist... » read more

Blog Review: May 13


Siemens' Loay Hegazy, Mohamed Taher, and Sherif Hammouda describe a GPU rasterizer designed specifically for computational lithography and present benchmark results and practical implications for mask synthesis workflows. Cadence's Udaya Shankar introduces RTL, logic, and physical restructuring techniques and how they can help improve PPA, reduce dynamic power consumption, and optimize place... » read more

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