tag: Keysight

Blog Review: May 20
By Jesse Allen - 20 May, 2026 - Comments: 0

Cadence's Siddh Virani demonstrates how to import and integrate foreign language logic into PSS on both Target and Solve platforms, opening possibilities for code reuse and cross-language collaboration. Synopsys' Sumit Vishwakarma finds that AI model training and inference workloads are forcing the industry to rethink not only how much compute fits in a rack, but how servers are architected ... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Chip Industry Week in Review
By The SE Staff - 15 May, 2026 - Comments: 0

Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

Blog Review: May 13
By Jesse Allen - 13 May, 2026 - Comments: 0

Siemens' Loay Hegazy, Mohamed Taher, and Sherif Hammouda describe a GPU rasterizer designed specifically for computational lithography and present benchmark results and practical implications for mask synthesis workflows. Cadence's Udaya Shankar introduces RTL, logic, and physical restructuring techniques and how they can help improve PPA, reduce dynamic power consumption, and optimize place... » read more

Chip Industry Week In Review
By The SE Staff - 08 May, 2026 - Comments: 0

Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

How OCP S.O.L.I.D. Completes The Data Center Security Picture
By Jasper van Woudenberg - 07 May, 2026 - Comments: 0

In 2023, the Open Compute Project launched S.A.F.E. (Security Appraisal Framework and Enablement), a standardized process for auditing data center hardware and firmware. It delivered something the industry needed: approved third-party reviewers, continuous assessments, and public reports — not just one-time certifications. S.A.F.E. provided the audit framework; what it did not provide was gui... » read more

Blog Review: May 6
By Jesse Allen - 06 May, 2026 - Comments: 0

Synopsys' Prith Banerjee identifies key challenges in designing AI data centers and why addressing them requires a transformative approach that impacts every aspect of the system design and its individual components. Cadence's Meet S Chauhan checks out what's new in MIPI C-PHY v3.0, including the new 18 wire state mode that can support high-resolution display and image sensors and motion vec... » read more

The Unavoidable CMMC Deadline
By Keysight - 06 May, 2026 - Comments: 0

The U.S. Department of Defense’s (DoD) Cybersecurity Maturity Model Certification (CMMC) rollout is no longer a future concern. It is rapidly becoming a contract eligibility requirement with a fixed end date. This solution brief, drawn from Keysight’s commissioned primary research on CMMC readiness across the Defense Industrial Base (DIB), explains why the deadline is unavoidable and why or... » read more

Chip Industry Week in Review
By The SE Staff - 01 May, 2026 - Comments: 0

Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

How To Streamline Your Advanced Package Interconnect Designs
By Maria Castillo - 30 Apr, 2026 - Comments: 0

Monolithic system-on-chip (SoC) designs was once a popular choice. However, they face significant constraints in the era of AI. By forcing all chip functions into a single die and process node, they reduce engineering, manufacturing, and design cost flexibility. In contrast, the multi-die nature of chiplets enables different SoC functions to be designed and verified independently and fabrica... » read more

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