generic structure in systemverilog

Question

I have an interface with multiple ports, 2 of the ports are structures:

I want to be able to use any structure that I need with my interface, is there any option in SystemVerilog which allows this?

I searched for generic structures but couldn't find any results.

this is an example of my interface:

interface My_Interface;

typedef struct {
    logic something;
} str1;

typedef struct {
    logic something;
} str2;

logic [15:0] data;      
logic [3:0] data2;      
logic wr_str1;
logic wr_str2;
str1 str1_r;
str2 str2_r;

endinterface:My_Interface

I have something like 30 structures, I want to be able to use whatever structure I want from these, the structures are different. they have different fields.

Answer 1

As dave_59 mentioned, there are no generic structs in verilog. But you can parameterize an interface with a type parameter as in the following example:

interface a_if #(type T = int)(input T svar);
endinterface

module top;
  int p1;
  a_if simple(p1); // default type is 'int'

  bit [3:0] p2;
  a_if#(.T(bit[3:0])) bit3(p2);

  typedef struct packed {
    logic a,b,c;
  } S;
  S p3;
  a_if#(.T(S)) sif(p3);

endmodule

The above allows you to have ports and non-ports of a type defined at the interface instantiation.