cannot elaborate instantiated module in verilog

Question

I'm trying to make a 4-bit full adder in Verilog. However, it seems that the fulladder cannot be instantiated. I cannot track the error either.

`timescale 1 ns / 1 ps

module halfadder(input a, input b, output s, output c);
    xor (s, a, b);
    and (c, a, b);
endmodule

module fulladder(input cin, input a, input b, output s, output c);
wire c1, s1, c2;

    halfadder (a, b, s1, c1);
    halfadder (cin, s1, s, c2);

    or (c, c1, c2);

endmodule

module bitadder(input cin, input [3:0] a, input [3:0] b, output [3:0] s, output c);
wire c0,c1,c2;

    fulladder (cin, a[0], b[0], s[0], c0);
    fulladder (c0, a[1], b[1], s[1], c1);
    fulladder (c1, a[2], b[2], s[2], c2);
    fulladder (c2, a[3], b[3], s[3], c);

endmodule

Answer 1

You need to add instance names for instances of all your modules: halfadder and fulladder.

module fulladder(input cin, input a, input b, output s, output c);
wire c1, s1, c2;

    halfadder ha0 (a, b, s1, c1);
    halfadder ha1 (cin, s1, s, c2);

    or (c, c1, c2);

endmodule

module bitadder(input cin, input [3:0] a, input [3:0] b, output [3:0] s, output c);
wire c0,c1,c2;

    fulladder fa0 (cin, a[0], b[0], s[0], c0);
    fulladder fa1 (c0, a[1], b[1], s[1], c1);
    fulladder fa2 (c1, a[2], b[2], s[2], c2);
    fulladder fa3 (c2, a[3], b[3], s[3], c);

endmodule

Instance names for primitives (xor, etc.) are optional.