Instantiation of a module in verilog

Question

I am getting an error in instantiating a module in verilog file. I am instantiating like this:

module lab3(input clk,set,reset,plus,minus,start,button,output reg [3:0]led,output reg [6:0]y);

wire [3:0] indicesgu[3:0];
reg [1:0] going;
reg alsogoing,yes;


if (going==1 && alsogoing)
begin
 up_counter up_0 
 indicesgu  ,
 indices    ,
 alsogoing
 );
end

and my up_counter module starts as:

module up_counter(input [3:0] indices_in [3:0],output [3:0]indices[3:0],output alsogoing);

reg [3:0]indices[3:0];
reg [2:0]current,setting;

when I try to compile in Xilinx, it says unexpected token up_counter. Thanks in advance.

toolic · Accepted Answer · 2013-01-25 13:30:26Z

2

There are several problems with your lab3 module.

You need an endmodule at the end.
You should not instantiate up_counter inside an if. Verilog does not support conditional instances like that.
You need an opening paren after the instance name up_0.

answered Jan 25, 2013 at 13:30

toolic

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Comments

vermaete · Accepted Answer · 2013-01-25 13:31:38Z

1

You have (multiple) syntax errors in your code. One of them is you need brackets () around your component port list

up_counter up_0 (indicesgu  ,
                 indices    ,
                 alsogoing
                 );

check the Verilog syntax for more info.

This will at least fix the 'unexpected token up_counter' error.

answered Jan 25, 2013 at 13:31

vermaete

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1 Comment

cauthon14 Over a year ago

Thanks. But it still says unexpected token up_counter. Actually, both of these modules are in two different files. I have added both of them as sources, but for some reason Xilinx does not recognize that one of them is being used in another.

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